X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP2041RDB.h;h=e196f3ce33ab32cbc97fbf0104eb2f2ca749960a;hb=abf9e5d0f2cd123951dfae0d5605b54394721b97;hp=f196ccf122e3bc40efc5b1870c71d7a8eaf91847;hpb=e5d5d4474ace2136009139e264b8edf2cddb13cb;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index f196ccf..e196f3c 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2011-2012 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -11,11 +10,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P2041RDB -#define CONFIG_PHYS_64BIT -#define CONFIG_DISPLAY_BOARDINFO -#define CONFIG_PPC_P2041 - #ifdef CONFIG_RAMBOOT_PBL #define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc @@ -29,32 +23,20 @@ #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc -#define CONFIG_SYS_NO_FLASH #endif /* High Level Configuration Options */ -#define CONFIG_BOOKE -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_E500MC /* BOOKE e500mc family */ #define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ -#define CONFIG_MP /* support multiple processors */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif #define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ -#define CONFIG_SYS_NUM_CPC CONFIG_NUM_DDR_CONTROLLERS -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ -#define CONFIG_PCI /* Enable PCI/PCIE */ -#define CONFIG_PCIE1 /* PCIE controler 1 */ -#define CONFIG_PCIE2 /* PCIE controler 2 */ -#define CONFIG_PCIE3 /* PCIE controler 3 */ +#define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS +#define CONFIG_PCIE1 /* PCIE controller 1 */ +#define CONFIG_PCIE2 /* PCIE controller 2 */ +#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ @@ -64,50 +46,26 @@ #define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ - #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_SYS_NO_FLASH -#if !defined(CONFIG_RAMBOOT_PBL) && !defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_IS_NOWHERE -#endif -#else -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE -#endif - #if defined(CONFIG_SPIFLASH) - #define CONFIG_SYS_EXTRA_ENV_RELOC - #define CONFIG_ENV_IS_IN_SPI_FLASH - #define CONFIG_ENV_SPI_BUS 0 - #define CONFIG_ENV_SPI_CS 0 - #define CONFIG_ENV_SPI_MAX_HZ 10000000 - #define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_SIZE 0x2000 /* 8KB */ #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #elif defined(CONFIG_SDCARD) - #define CONFIG_SYS_EXTRA_ENV_RELOC - #define CONFIG_ENV_IS_IN_MMC #define CONFIG_FSL_FIXED_MMC_LOCATION #define CONFIG_SYS_MMC_ENV_DEV 0 #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_OFFSET (512 * 1658) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_EXTRA_ENV_RELOC -#define CONFIG_ENV_IS_IN_NAND #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_OFFSET (7 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) -#define CONFIG_ENV_IS_IN_REMOTE #define CONFIG_ENV_ADDR 0xffe20000 #define CONFIG_ENV_SIZE 0x2000 #elif defined(CONFIG_ENV_IS_NOWHERE) #define CONFIG_ENV_SIZE 0x2000 #else - #define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE \ - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 @@ -137,8 +95,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x00400000 -#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_PANIC_HANG /* do not reset board on panic */ /* * Config the L3 Cache as L3 SRAM @@ -176,7 +132,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL (4 * CONFIG_DIMM_SLOTS_PER_CTLR) #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 @@ -250,7 +205,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ @@ -288,10 +242,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_MISC_INIT_R - #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ @@ -323,7 +273,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * open - index 2 * shorted - index 1 */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0)/2) @@ -336,18 +285,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_CCSRBAR+0x11D500) #define CONFIG_SYS_NS16550_COM4 (CONFIG_SYS_CCSRBAR+0x11D600) -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT -#define CONFIG_OF_BOARD_SETUP -#define CONFIG_OF_STDOUT_VIA_ALIAS - -/* new uImage format support */ -#define CONFIG_FIT -#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ - /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL @@ -409,10 +346,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * eSPI - Enhanced SPI */ -#define CONFIG_SPI_FLASH_SPANSION -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE 0 /* * General PCI @@ -477,7 +410,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* Support Q/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 #define CONFIG_SYS_BMAN_MEM_BASE 0xf4000000 #ifdef CONFIG_PHYS_64BIT @@ -519,7 +451,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); * env is stored at 0x100000, sector size is 0x10000, ucode is stored after * env, so we got 0x110000. */ -#define CONFIG_SYS_QE_FW_IN_SPIFLASH #define CONFIG_SYS_FMAN_FW_ADDR 0x110000 #elif defined(CONFIG_SDCARD) /* @@ -527,10 +458,8 @@ unsigned long get_board_sys_clk(unsigned long dummy); * about 825KB (1650 blocks), Env is stored after the image, and the env size is * 0x2000 (16 blocks), 8 + 1650 + 16 = 1674, enlarge it to 1680. */ -#define CONFIG_SYS_QE_FMAN_FW_IN_MMC #define CONFIG_SYS_FMAN_FW_ADDR (512 * 1680) #elif defined(CONFIG_NAND) -#define CONFIG_SYS_QE_FMAN_FW_IN_NAND #define CONFIG_SYS_FMAN_FW_ADDR (8 * CONFIG_SYS_NAND_BLOCK_SIZE) #elif defined(CONFIG_SRIO_PCIE_BOOT_SLAVE) /* @@ -540,17 +469,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); * slave SRIO or PCIE outbound window->master inbound window-> * master LAW->the ucode address in master's memory space. */ -#define CONFIG_SYS_QE_FMAN_FW_IN_REMOTE #define CONFIG_SYS_FMAN_FW_ADDR 0xFFE00000 #else -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_FMAN_FW_ADDR 0xEFF00000 #endif #define CONFIG_SYS_QE_FMAN_FW_LENGTH 0x10000 #define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) #ifdef CONFIG_SYS_DPAA_FMAN -#define CONFIG_FMAN_ENET #define CONFIG_PHYLIB_10G #define CONFIG_PHY_VITESSE #define CONFIG_PHY_TERANETICS @@ -558,19 +484,14 @@ unsigned long get_board_sys_clk(unsigned long dummy); #ifdef CONFIG_PCI #define CONFIG_PCI_INDIRECT_BRIDGE -#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION #endif /* CONFIG_PCI */ /* SATA */ #define CONFIG_FSL_SATA_V2 #ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_FSL_SATA -#define CONFIG_LIBATA - #define CONFIG_SYS_SATA_MAX_DEVICE 2 #define CONFIG_SATA1 #define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR @@ -580,9 +501,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA #define CONFIG_LBA48 -#define CONFIG_CMD_SATA -#define CONFIG_DOS_PARTITION -#define CONFIG_CMD_EXT2 #endif #ifdef CONFIG_FMAN_ENET @@ -600,9 +518,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_FM1_10GEC1_PHY_ADDR 0 #define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC1" -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #endif /* @@ -614,17 +530,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* * Command line configuration. */ -#define CONFIG_CMD_DHCP -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_GREPENV -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_I2C -#define CONFIG_CMD_MII -#define CONFIG_CMD_PING - -#ifdef CONFIG_PCI -#define CONFIG_CMD_PCI -#endif /* * USB @@ -633,52 +538,19 @@ unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_HAS_FSL_MPH_USB #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB) -#define CONFIG_CMD_USB -#define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #endif -#define CONFIG_CMD_EXT2 - -#define CONFIG_MMC - #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT -#define CONFIG_CMD_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#endif - -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL #endif /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#ifdef CONFIG_CMD_KGDB -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ - sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * For booting Linux, the board info and command line data @@ -702,10 +574,6 @@ unsigned long get_board_sys_clk(unsigned long dummy); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - #define __USB_PHY_TYPE utmi #define CONFIG_EXTRA_ENV_SETTINGS \ @@ -725,7 +593,7 @@ unsigned long get_board_sys_clk(unsigned long dummy); "usb_dr_mode=host\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2041rdb/ramdisk.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p2041rdb/p2041rdb.dtb\0" \ "bdev=sda3\0" @@ -757,8 +625,4 @@ unsigned long get_board_sys_clk(unsigned long dummy); #include -#ifdef CONFIG_SECURE_BOOT -#define CONFIG_CMD_BLOB -#endif - #endif /* __CONFIG_H */