X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP2041RDB.h;h=08c1bccb2b74ad65998d4bc79fef6c827da96ec7;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=dfe92bcea0996239be6810e15b938c6c10ff2e28;hpb=e78e880da9e9f85a9b901385fa1d6d37b9f60d2d;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index dfe92bc..08c1bcc 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -12,30 +12,25 @@ #define __CONFIG_H #ifdef CONFIG_RAMBOOT_PBL -#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_RAMBOOT_TEXT_BASE CONFIG_TEXT_BASE #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif #ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* Set 1M boot space */ -#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_SYS_TEXT_BASE & 0xfff00000) +#define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR (CONFIG_TEXT_BASE & 0xfff00000) #define CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR_PHYS \ (0x300000000ull | CONFIG_SYS_SRIO_PCIE_BOOT_SLAVE_ADDR) #define CONFIG_RESET_VECTOR_ADDRESS 0xfffffffc #endif /* High Level Configuration Options */ -#define CONFIG_SYS_BOOK3E_HV /* Category E.HV supported */ #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCIE1 /* PCIE controller 1 */ -#define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ @@ -43,11 +38,6 @@ #define CONFIG_SRIO_PCIE_BOOT_MASTER #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#if defined(CONFIG_SPIFLASH) -#elif defined(CONFIG_SDCARD) - #define CONFIG_FSL_FIXED_MMC_LOCATION -#endif - #ifndef __ASSEMBLY__ #include #endif @@ -55,11 +45,8 @@ /* * These can be toggled for performance analysis, otherwise use default. */ -#define CONFIG_SYS_CACHE_STASHING #define CONFIG_SYS_INIT_L2CSR0 L2CSR0_L2E -#define CONFIG_ENABLE_36BIT_PHYS - #define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ /* @@ -72,18 +59,12 @@ #else #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR #endif -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE) #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull #endif -/* EEPROM */ -#define CONFIG_SYS_I2C_EEPROM_NXID -#define CONFIG_SYS_EEPROM_BUS_NUM 0 - /* * DDR Setup */ @@ -91,7 +72,6 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x52 #define CONFIG_SYS_SDRAM_SIZE 4096 /* for fixed parameter use */ @@ -114,13 +94,6 @@ #define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE #endif -#define CONFIG_SYS_FLASH_BR_PRELIM \ - (BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \ - BR_PS_16 | BR_V) -#define CONFIG_SYS_FLASH_OR_PRELIM \ - ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \ - | OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR) - #define CONFIG_FSL_CPLD #define CPLD_BASE 0xffdf0000 /* CPLD registers */ #ifdef CONFIG_PHYS_64BIT @@ -134,17 +107,8 @@ #define PIXIS_LBMAP_SHIFT 4 #define PIXIS_LBMAP_ALTBANK 0x40 -#define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */ -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Write Timeout (ms) */ - -#if defined(CONFIG_RAMBOOT_PBL) -#define CONFIG_SYS_RAMBOOT -#endif - /* Nand Flash */ #ifdef CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BASE 0xffa00000 @@ -155,7 +119,6 @@ #endif #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* NAND flash config */ #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ @@ -173,14 +136,12 @@ | OR_FCM_EHTR) #endif /* CONFIG_NAND_FSL_ELBC */ -#define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000} #define CONFIG_HWCONFIG /* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf @@ -198,8 +159,6 @@ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 @@ -330,25 +289,6 @@ #define CONFIG_SYS_DPAA_FMAN #define CONFIG_SYS_DPAA_PME -#define CONFIG_SYS_FDT_PAD (0x3000 + CONFIG_SYS_QE_FMAN_FW_LENGTH) - -#ifdef CONFIG_PCI -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#endif /* CONFIG_PCI */ - -/* SATA */ -#define CONFIG_FSL_SATA_V2 - -#ifdef CONFIG_FSL_SATA_V2 -#define CONFIG_SATA1 -#define CONFIG_SYS_SATA1 CONFIG_SYS_MPC85xx_SATA1_ADDR -#define CONFIG_SYS_SATA1_FLAGS FLAGS_DMA -#define CONFIG_SATA2 -#define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR -#define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA - -#define CONFIG_LBA48 -#endif #ifdef CONFIG_FMAN_ENET #define CONFIG_SYS_FM1_DTSEC1_PHY_ADDR 0x2 @@ -367,21 +307,8 @@ #define CONFIG_SYS_TBIPA_VALUE 8 #endif -/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - -/* -* USB -*/ -#define CONFIG_HAS_FSL_DR_USB -#define CONFIG_HAS_FSL_MPH_USB - #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR -#define CONFIG_SYS_FSL_ESDHC_BROKEN_TIMEOUT +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif /* @@ -394,7 +321,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration @@ -409,7 +335,7 @@ "bank_intlv=cs0_cs1\0" \ "netdev=eth0\0" \ "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ - "ubootaddr=" __stringify(CONFIG_SYS_TEXT_BASE) "\0" \ + "ubootaddr=" __stringify(CONFIG_TEXT_BASE) "\0" \ "tftpflash=tftpboot $loadaddr $uboot && " \ "protect off $ubootaddr +$filesize && " \ "erase $ubootaddr +$filesize && " \