X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP2020DS.h;h=d7d64d2936180a7d847a7f13620f8abb4e3800e0;hb=219f4788d33b04e394d4ade1feaedc0292acc790;hp=30a5a319bcc634719a4afaba451447e8585b5e9b;hpb=ca02f6f8dc4966b2a019b15e01b5070189327df2;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P2020DS.h b/include/configs/P2020DS.h index 30a5a31..d7d64d2 100644 --- a/include/configs/P2020DS.h +++ b/include/configs/P2020DS.h @@ -1,5 +1,5 @@ /* - * Copyright 2007-2009 Freescale Semiconductor, Inc. + * Copyright 2007-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -27,10 +27,26 @@ #ifndef __CONFIG_H #define __CONFIG_H -#ifdef CONFIG_MK_36BIT +#include "../board/freescale/common/ics307_clk.h" + +#ifdef CONFIG_36BIT #define CONFIG_PHYS_64BIT #endif +#ifdef CONFIG_SDCARD +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#define CONFIG_SYS_TEXT_BASE 0xf8f80000 +#define CONFIG_RESET_VECTOR_ADDRESS 0xf8fffffc +#endif + /* High Level Configuration Options */ #define CONFIG_BOOKE 1 /* BOOKE */ #define CONFIG_E500 1 /* BOOKE e500 family */ @@ -39,6 +55,18 @@ #define CONFIG_P2020DS 1 #define CONFIG_MP 1 /* support multiple processors */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ +#define CONFIG_SRIO2 /* SRIO port 2 */ + #define CONFIG_FSL_ELBC 1 /* Has Enhanced localbus controller */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controler 1 (slot 1) */ @@ -54,17 +82,9 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE -#ifndef __ASSEMBLY__ -extern unsigned long calculate_board_sys_clk(unsigned long dummy); -extern unsigned long calculate_board_ddr_clk(unsigned long dummy); -/* extern unsigned long get_board_sys_clk(unsigned long dummy); */ -/* extern unsigned long get_board_ddr_clk(unsigned long dummy); */ -#endif -#define CONFIG_SYS_CLK_FREQ calculate_board_sys_clk(0) /* sysclk for MPC85xx */ -#define CONFIG_DDR_CLK_FREQ calculate_board_ddr_clk(0) /* ddrclk for MPC85xx */ +#define CONFIG_SYS_CLK_FREQ get_board_sys_clk() /* sysclk for MPC85xx */ +#define CONFIG_DDR_CLK_FREQ get_board_ddr_clk() /* ddrclk for MPC85xx */ #define CONFIG_ICS307_REFCLK_HZ 33333000 /* ICS307 clock chip ref freq */ -#define CONFIG_GET_CLK_FROM_ICS307 /* decode sysclk and ddrclk freq - from ICS307 instead of switches */ /* * These can be toggled for performance analysis, otherwise use default. @@ -72,6 +92,8 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ +#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ + #define CONFIG_ENABLE_36BIT_PHYS 1 #ifdef CONFIG_PHYS_64BIT @@ -79,30 +101,33 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ #endif -#define CONFIG_SYS_MEMTEST_START 0x00000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x7fffffff +#define CONFIG_POST CONFIG_SYS_POST_MEMORY /* test POST memory test */ +#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x00400000 #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) + * Config the L2 Cache */ -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ -#define CONFIG_SYS_CCSRBAR 0xffe00000 /* relocated CCSRBAR */ +#define CONFIG_SYS_INIT_L2_ADDR 0xf8f80000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_CCSRBAR_PHYS 0xfffe00000ull /* physical addr of CCSRBAR */ +#define CONFIG_SYS_INIT_L2_ADDR_PHYS 0xff8f80000ull #else -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ +#define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR #endif -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ +#define CONFIG_SYS_L2_SIZE (512 << 10) +#define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -#define CONFIG_SYS_PCIE3_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCIE2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ #define CONFIG_VERY_BIG_RAM +#ifdef CONFIG_DDR2 +#define CONFIG_FSL_DDR2 +#else #define CONFIG_FSL_DDR3 1 +#endif #undef CONFIG_FSL_DDR_INTERACTIVE /* ECC will be enabled based on perf_mode environment variable */ @@ -119,8 +144,9 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CHIP_SELECTS_PER_CTRL 2 /* I2C addresses of SPD EEPROMs */ +#define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 0 /* SPD EEPROM located on I2C bus 0 */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1GB */ @@ -229,7 +255,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -238,7 +264,10 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ -#define CONFIG_FSL_PIXIS 1 /* use common PIXIS code */ +#define CONFIG_HWCONFIG /* enable hwconfig */ +#define CONFIG_FSL_NGPIXIS /* use common ngPIXIS code */ + +#ifdef CONFIG_FSL_NGPIXIS #define PIXIS_BASE 0xffdf0000 /* PIXIS registers */ #ifdef CONFIG_PHYS_64BIT #define PIXIS_BASE_PHYS 0xfffdf0000ull @@ -249,66 +278,29 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V) #define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */ -#define PIXIS_ID 0x0 /* Board ID at offset 0 */ -#define PIXIS_VER 0x1 /* Board version at offset 1 */ -#define PIXIS_PVER 0x2 /* PIXIS FPGA version at offset 2 */ -#define PIXIS_CSR 0x3 /* PIXIS General control/status register */ -#define PIXIS_RST 0x4 /* PIXIS Reset Control register */ -#define PIXIS_PWR 0x5 /* PIXIS Power status register */ -#define PIXIS_AUX 0x6 /* Auxiliary 1 register */ -#define PIXIS_SPD 0x7 /* Register for SYSCLK speed */ -#define PIXIS_AUX2 0x8 /* Auxiliary 2 register */ -#define PIXIS_VCTL 0x10 /* VELA Control Register */ -#define PIXIS_VSTAT 0x11 /* VELA Status Register */ -#define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ -#define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ -#define PIXIS_VCORE0 0x14 /* VELA VCORE0 Register */ -#define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ -#define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ -#define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ -#define PIXIS_VSPEED2 0x19 /* VELA VSpeed 2 */ -#define PIXIS_VSYSCLK0 0x19 /* VELA SYSCLK0 Register */ -#define PIXIS_VSYSCLK1 0x1A /* VELA SYSCLK1 Register */ -#define PIXIS_VSYSCLK2 0x1B /* VELA SYSCLK2 Register */ -#define PIXIS_VDDRCLK0 0x1C /* VELA DDRCLK0 Register */ -#define PIXIS_VDDRCLK1 0x1D /* VELA DDRCLK1 Register */ -#define PIXIS_VDDRCLK2 0x1E /* VELA DDRCLK2 Register */ - -#define PIXIS_VWATCH 0x24 /* Watchdog Register */ -#define PIXIS_LED 0x25 /* LED Register */ - -#define PIXIS_SW(x) 0x20 + (x - 1) * 2 -#define PIXIS_EN(x) 0x21 + (x - 1) * 2 -#define PIXIS_SW7_LBMAP 0xc0 /* SW7 - cfg_lbmap */ -#define PIXIS_SW7_VBANK 0x30 /* SW7 - cfg_vbank */ - -/* old pixis referenced names */ -#define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ -#define PIXIS_VCLKL 0x1A /* VELA VCLKL register */ -#define CONFIG_SYS_PIXIS_VBOOT_MASK 0xc0 -#define PIXIS_VSPEED2_TSEC1SER 0x8 -#define PIXIS_VSPEED2_TSEC2SER 0x4 -#define PIXIS_VSPEED2_TSEC3SER 0x2 -#define PIXIS_VSPEED2_TSEC4SER 0x1 -#define PIXIS_VCFGEN1_TSEC1SER 0x20 -#define PIXIS_VCFGEN1_TSEC2SER 0x20 -#define PIXIS_VCFGEN1_TSEC3SER 0x20 -#define PIXIS_VCFGEN1_TSEC4SER 0x20 -#define PIXIS_VSPEED2_MASK (PIXIS_VSPEED2_TSEC1SER \ - | PIXIS_VSPEED2_TSEC2SER \ - | PIXIS_VSPEED2_TSEC3SER \ - | PIXIS_VSPEED2_TSEC4SER) -#define PIXIS_VCFGEN1_MASK (PIXIS_VCFGEN1_TSEC1SER \ - | PIXIS_VCFGEN1_TSEC2SER \ - | PIXIS_VCFGEN1_TSEC3SER \ - | PIXIS_VCFGEN1_TSEC4SER) +#define PIXIS_LBMAP_SWITCH 7 +#define PIXIS_LBMAP_MASK 0xf0 +#define PIXIS_LBMAP_SHIFT 4 +#define PIXIS_LBMAP_ALTBANK 0x20 +#endif #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ -#define CONFIG_SYS_INIT_RAM_END 0x00004000 /* End of used area in RAM */ +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR +/* The assembler doesn't like typecast */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS \ + ((CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH * 1ull << 32) | \ + CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) +#else +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS CONFIG_SYS_INIT_RAM_ADDR /* Initial L1 address */ +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0 +#define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW CONFIG_SYS_INIT_RAM_ADDR_PHYS +#endif +#define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ @@ -331,12 +323,12 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) /* NAND flash config */ -#define CONFIG_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ +#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2< " -#endif /* * Pass open firmware flat tree @@ -424,11 +412,24 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_EEPROM_BUS_NUM 0 /* + * eSPI - Enhanced SPI + */ +#define CONFIG_FSL_ESPI + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION + +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +/* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ /* controller 3, Slot 1, tgtid 3, Base address b000 */ +#define CONFIG_SYS_PCIE3_NAME "Slot 1" #define CONFIG_SYS_PCIE3_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 @@ -448,6 +449,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ /* controller 2, direct to uli, tgtid 2, Base address 9000 */ +#define CONFIG_SYS_PCIE2_NAME "ULI" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 @@ -467,6 +469,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ /* controller 1, Slot 2, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 2" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xc0000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 @@ -504,7 +507,24 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_SYS_ISA_IO_BASE_ADDRESS VIDEO_IO_OFFSET #endif -#define CONFIG_NET_MULTI +/* SRIO1 uses the same window as PCIE2 mem window */ +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xa0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xc20000000ull +#else +#define CONFIG_SYS_SRIO1_MEM_PHYS 0xa0000000 +#endif +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ + +/* SRIO2 uses the same window as PCIE1 mem window */ +#define CONFIG_SYS_SRIO2_MEM_VIRT 0xc0000000 +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc40000000ull +#else +#define CONFIG_SYS_SRIO2_MEM_PHYS 0xc0000000 +#endif +#define CONFIG_SYS_SRIO2_MEM_SIZE 0x20000000 /* 512M */ + #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 @@ -534,10 +554,6 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 @@ -575,6 +591,21 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* * Environment */ +#if defined(CONFIG_SDCARD) +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_FSL_FIXED_MMC_LOCATION +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#elif defined(CONFIG_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_SIZE 0x2000 /* 8KB */ +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#else #define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 @@ -583,6 +614,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #endif #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ +#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -599,6 +631,7 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -610,19 +643,41 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* * USB */ +#define CONFIG_USB_EHCI + +#ifdef CONFIG_USB_EHCI #define CONFIG_CMD_USB #define CONFIG_USB_STORAGE -#define CONFIG_USB_EHCI #define CONFIG_USB_EHCI_FSL #define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ /* + * SDHC/MMC + */ +#define CONFIG_MMC + +#ifdef CONFIG_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_CMD_MMC +#define CONFIG_GENERIC_MMC +#endif + +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif + +/* * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -637,18 +692,11 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -662,20 +710,15 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); /* The mac addresses for all ethernet interface */ #if defined(CONFIG_TSEC_ENET) #define CONFIG_HAS_ETH0 -#define CONFIG_ETHADDR 00:E0:0C:02:00:FD #define CONFIG_HAS_ETH1 -#define CONFIG_ETH1ADDR 00:E0:0C:02:01:FD #define CONFIG_HAS_ETH2 -#define CONFIG_ETH2ADDR 00:E0:0C:02:02:FD -#define CONFIG_HAS_ETH3 -#define CONFIG_ETH3ADDR 00:E0:0C:02:03:FD #endif #define CONFIG_IPADDR 192.168.1.254 #define CONFIG_HOSTNAME unknown -#define CONFIG_ROOTPATH /opt/nfsroot -#define CONFIG_BOOTFILE uImage +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_SERVERIP 192.168.1.1 @@ -691,28 +734,36 @@ extern unsigned long calculate_board_ddr_clk(unsigned long dummy); #define CONFIG_BAUDRATE 115200 #define CONFIG_EXTRA_ENV_SETTINGS \ - "perf_mode=stable\0" \ - "memctl_intlv_ctl=2\0" \ + "perf_mode=performance\0" \ + "hwconfig=fsl_ddr:ctlr_intlv=bank,bank_intlv=cs0_cs1;" \ + "usb1:dr_mode=host,phy_type=ulpi\0" \ "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ + "satabootcmd=setenv bootargs root=/dev/$bdev rw " \ + "console=$consoledev,$baudrate $othbootargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=p2020ds/ramdisk.uboot\0" \ "fdtaddr=c00000\0" \ + "othbootargs=cache-sram-size=0x10000\0" \ "fdtfile=p2020ds/p2020ds.dtb\0" \ - "bdev=sda3\0" + "bdev=sda3\0" \ + "partition=scsi 0:0\0" #define CONFIG_HDBOOT \ "setenv bootargs root=/dev/$bdev rw " \ "console=$consoledev,$baudrate $othbootargs;" \ - "tftp $loadaddr $bootfile;" \ - "tftp $fdtaddr $fdtfile;" \ + "ext2load $partition $loadaddr $bootfile;" \ + "ext2load $partition $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" #define CONFIG_NFSBOOTCOMMAND \