X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP1023RDB.h;h=4f6ee223853770714a83ee01a83ee2721b7fc50c;hb=4862830b696a6d0750e19d32a82553cdb41a85f8;hp=a53b1acdf68807198963802d9d91b6937074e742;hpb=9f0f432c0aea1e70959a0c06938459d3175a36b0;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P1023RDB.h b/include/configs/P1023RDB.h index a53b1ac..4f6ee22 100644 --- a/include/configs/P1023RDB.h +++ b/include/configs/P1023RDB.h @@ -1,21 +1,14 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013 Freescale Semiconductor, Inc. * * Authors: Roy Zang * Chunhe Lan - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif @@ -25,21 +18,14 @@ #endif /* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_P1023 -#define CONFIG_MP /* support multiple processors */ -#define CONFIG_FSL_ELBC /* Has Enhanced localbus controller */ -#define CONFIG_PCI /* Enable PCI/PCIE */ #define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ -#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controler 2 (slot 2) */ -#define CONFIG_PCIE3 /* PCIE controler 3 (slot 3) */ +#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ +#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ +#define CONFIG_PCIE3 /* PCIE controller 3 (slot 3) */ #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_FSL_LAW /* Use common FSL init code */ #ifndef __ASSEMBLY__ extern unsigned long get_clock_freq(void); @@ -60,8 +46,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MEMTEST_START 0x01000000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x02000000 -#define CONFIG_PANIC_HANG /* do not reset board on panic */ - /* Implement conversion of addresses in the LBC */ #define CONFIG_SYS_LBC_LBCR 0x00000000 #define CONFIG_SYS_LBC_LCRR LCRR_CLKDIV_8 @@ -75,8 +59,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL 1 #define CONFIG_DDR_SPD -#define CONFIG_SYS_FSL_DDR3 -#define CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SYS_SDRAM_SIZE 512u /* DDR is 512M */ #define CONFIG_SYS_SPD_BUS_NUM 0 #define SPD_EEPROM_ADDRESS 0x50 @@ -109,17 +91,12 @@ extern unsigned long get_clock_freq(void); | BR_PS_16 | BR_V) #define CONFIG_FLASH_OR_PRELIM 0xfc000ff7 -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 512 /* sectors per device */ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_BOARD_EARLY_INIT_F /* call board_early_init_f function */ -#define CONFIG_BOARD_EARLY_INIT_R /* call board_early_init_r function */ - #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000/* Size of used area in RAM */ @@ -135,7 +112,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND #define CONFIG_NAND_FSL_ELBC #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) @@ -160,7 +136,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */ /* Serial Port */ -#define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -172,9 +147,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR + 0x4500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR + 0x4600) -/* Use the HUSH parser */ -#define CONFIG_SYS_HUSH_PARSER - /* I2C */ #define CONFIG_SYS_I2C #define CONFIG_SYS_I2C_FSL @@ -196,8 +168,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_BUS_NUM 0 -#define CONFIG_CMD_I2C - /* * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. @@ -237,7 +207,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #if defined(CONFIG_PCI) -#define CONFIG_PCI_PNP /* do pci plug-and-play */ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */ @@ -246,7 +215,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENV_OVERWRITE -#define CONFIG_ENV_IS_IN_FLASH #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) */ @@ -255,52 +223,20 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ /* - * Command line configuration. - */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_PING -#define CONFIG_CMD_MII -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) -#define CONFIG_CMD_PCI -#endif - -/* * USB */ #define CONFIG_HAS_FSL_DR_USB #ifdef CONFIG_HAS_FSL_DR_USB -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI -#define CONFIG_CMD_USB +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL -#define CONFIG_USB_STORAGE -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION #endif #endif /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT)+16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -/* Boot Argument Buffer Size */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* * For booting Linux, the board info and command line data @@ -319,12 +255,7 @@ extern unsigned long get_clock_freq(void); /* default location for tftp and bootm */ #define CONFIG_LOADADDR 1000000 -#define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ - -#define CONFIG_BAUDRATE 115200 - /* Qman/Bman */ -#define CONFIG_SYS_DPAA_QBMAN /* support Q/Bman */ #define CONFIG_SYS_QMAN_MEM_BASE 0xff000000 #define CONFIG_SYS_QMAN_MEM_PHYS CONFIG_SYS_QMAN_MEM_BASE #define CONFIG_SYS_QMAN_MEM_SIZE 0x00200000 @@ -350,7 +281,6 @@ extern unsigned long get_clock_freq(void); /* For FM */ #define CONFIG_SYS_DPAA_FMAN -#define CONFIG_PHY_GIGE /* Include GbE speed/duplex detection */ #ifdef CONFIG_SYS_DPAA_FMAN #define CONFIG_FMAN_ENET @@ -369,7 +299,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FM1_DTSEC2_PHY_ADDR 0x2 #define CONFIG_SYS_TBIPA_VALUE 8 -#define CONFIG_MII /* MII PHY management */ #define CONFIG_ETHPRIME "FM1@DTSEC1" #endif @@ -387,7 +316,7 @@ extern unsigned long get_clock_freq(void); "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=rootfs.ext2.gz.uboot\0" \ - "fdtaddr=c00000\0" \ + "fdtaddr=1e00000\0" \ "fdtfile=p1023rdb.dtb\0" \ "othbootargs=ramdisk_size=600000\0" \ "bdev=sda1\0" \