X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP1010RDB.h;h=baa83698c50ab3bfa5dcc1be69c1c55892af4ebf;hb=0ff27d4a94637d4b1937c625d33212375bd118d9;hp=c45b091227c6dbe71ae4d8153f7c8b89d6dd8721;hpb=c4762157cf49ae6556016267ec0a87d4aee9e572;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index c45b091..baa8369 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P1010 -#define CONFIG_E500 /* BOOKE e500 family */ #include #define CONFIG_NAND_FSL_IFC @@ -20,7 +18,6 @@ #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xD0001000 #define CONFIG_SPL_PAD_TO 0x18000 @@ -46,7 +43,6 @@ #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xD0001000 #define CONFIG_SPL_PAD_TO 0x18000 @@ -134,8 +130,6 @@ #endif /* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ #define CONFIG_FSL_IFC /* Enable IFC Support */ #define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ @@ -175,9 +169,9 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 @@ -199,10 +193,8 @@ #endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION #endif -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_TSEC_ENET #define CONFIG_ENV_OVERWRITE @@ -231,7 +223,6 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 @@ -379,7 +370,7 @@ extern unsigned long get_sdram_size(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -389,7 +380,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ @@ -405,7 +396,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ @@ -420,7 +411,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NAND_TWHRE(0x0f) #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ @@ -512,7 +503,6 @@ extern unsigned long get_sdram_size(void); #endif #endif -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_SYS_INIT_RAM_LOCK @@ -593,7 +583,7 @@ extern unsigned long get_sdram_size(void); #define I2C_PCA9557_BUS_NUM 0 /* I2C EEPROM */ -#if defined(CONFIG_P1010RDB_PB) +#if defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID @@ -677,11 +667,8 @@ extern unsigned long get_sdram_size(void); #define CONFIG_LBA48 #endif /* #ifdef CONFIG_FSL_SATA */ -#define CONFIG_MMC #ifdef CONFIG_MMC -#define CONFIG_DOS_PARTITION #define CONFIG_FSL_ESDHC -#define CONFIG_GENERIC_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif @@ -719,10 +706,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #else -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif @@ -754,7 +741,6 @@ extern unsigned long get_sdram_size(void); #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ || defined(CONFIG_FSL_SATA) -#define CONFIG_DOS_PARTITION #endif /* Hash command with SHA acceleration supported in hardware */ @@ -843,7 +829,7 @@ extern unsigned long get_sdram_size(void); "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ CONFIG_BOOTMODE -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ @@ -852,7 +838,7 @@ extern unsigned long get_sdram_size(void); "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \