X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP1010RDB.h;h=addb306d57fc5af55277f882506d45bacf8f4c0e;hb=6cc04547cb3bbd3a3d78947f200acbae19e3c67f;hp=19aebb810c7bb507d344b74d4eed72b7e81749d6;hpb=f4cd75e96a461e1b138c3af85a4085e2772e4f7c;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 19aebb8..addb306 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -63,9 +63,6 @@ /* High Level Configuration Options */ #if defined(CONFIG_PCI) -#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ -#define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ - /* * PCI Windows * Memory space is mapped 1-1, but I/O space must start from 0. @@ -97,8 +94,6 @@ #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif - -#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif #define CONFIG_HWCONFIG @@ -119,44 +114,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -/* DDR3 Controller Settings */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000003f -#define CONFIG_SYS_DDR_CS0_CONFIG 0x80014302 -#define CONFIG_SYS_DDR_CS0_CONFIG_2 0x00000000 -#define CONFIG_SYS_DDR_DATA_INIT 0xdeadbeef -#define CONFIG_SYS_DDR_INIT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_INIT_EXT_ADDR 0x00000000 -#define CONFIG_SYS_DDR_MODE_CONTROL 0x00000000 -#define CONFIG_SYS_DDR_ZQ_CONTROL 0x89080600 -#define CONFIG_SYS_DDR_SR_CNTR 0x00000000 -#define CONFIG_SYS_DDR_RCW_1 0x00000000 -#define CONFIG_SYS_DDR_RCW_2 0x00000000 -#define CONFIG_SYS_DDR_CONTROL 0xc70c0008 /* Type = DDR3 */ -#define CONFIG_SYS_DDR_CONTROL_2 0x24401000 -#define CONFIG_SYS_DDR_TIMING_4 0x00000001 -#define CONFIG_SYS_DDR_TIMING_5 0x03402400 - -#define CONFIG_SYS_DDR_TIMING_3_800 0x00030000 -#define CONFIG_SYS_DDR_TIMING_0_800 0x00110104 -#define CONFIG_SYS_DDR_TIMING_1_800 0x6f6b8644 -#define CONFIG_SYS_DDR_TIMING_2_800 0x0FA888CF -#define CONFIG_SYS_DDR_CLK_CTRL_800 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_800 0x00441420 -#define CONFIG_SYS_DDR_MODE_2_800 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_800 0x0C300100 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_800 0x8675f608 - -/* settings for DDR3 at 667MT/s */ -#define CONFIG_SYS_DDR_TIMING_3_667 0x00010000 -#define CONFIG_SYS_DDR_TIMING_0_667 0x00110004 -#define CONFIG_SYS_DDR_TIMING_1_667 0x5d59e544 -#define CONFIG_SYS_DDR_TIMING_2_667 0x0FA890CD -#define CONFIG_SYS_DDR_CLK_CTRL_667 0x03000000 -#define CONFIG_SYS_DDR_MODE_1_667 0x00441210 -#define CONFIG_SYS_DDR_MODE_2_667 0x00000000 -#define CONFIG_SYS_DDR_INTERVAL_667 0x0a280000 -#define CONFIG_SYS_DDR_WRLVL_CONTROL_667 0x8675F608 - #define CONFIG_SYS_CCSRBAR 0xffe00000 #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR @@ -180,7 +137,6 @@ extern unsigned long get_sdram_size(void); /* NOR Flash on IFC */ #define CONFIG_SYS_FLASH_BASE 0xee000000 -#define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) @@ -206,15 +162,9 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_NOR_FTIM3 0x0 #define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS} -#define CONFIG_SYS_FLASH_QUIET_TEST #define CONFIG_FLASH_SHOW_PROGRESS 45 /* count down from 45/5: 9..1 */ -#undef CONFIG_SYS_FLASH_CHECKSUM -#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ -#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ - /* CFI for NOR Flash */ -#define CONFIG_SYS_FLASH_EMPTY_INFO /* NAND Flash on IFC */ #define CONFIG_SYS_NAND_BASE 0xff800000 @@ -252,7 +202,6 @@ extern unsigned long get_sdram_size(void); #endif #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ @@ -347,20 +296,11 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0 -#if defined(CONFIG_RAMBOOT_SDCARD) || defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_SYS_RAMBOOT -#else -#undef CONFIG_SYS_RAMBOOT -#endif - -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */ #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - /* * Config the L2 Cache as L2 SRAM */ @@ -368,18 +308,15 @@ extern unsigned long get_sdram_size(void); #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #endif @@ -407,10 +344,6 @@ extern unsigned long get_sdram_size(void); /* I2C EEPROM */ #if defined(CONFIG_TARGET_P1010RDB_PB) -#ifdef CONFIG_ID_EEPROM -#define CONFIG_SYS_I2C_EEPROM_NXID -#endif -#define CONFIG_SYS_EEPROM_BUS_NUM 0 #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ #endif /* enable read and write access to EEPROM */ @@ -459,23 +392,18 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */ #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif /* * Environment */ -#if defined(CONFIG_SDCARD) -#define CONFIG_FSL_FIXED_MMC_LOCATION -#elif defined(CONFIG_MTD_RAW_NAND) +#if defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define SPL_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #endif #endif -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ || defined(CONFIG_FSL_SATA) #endif @@ -490,7 +418,6 @@ extern unsigned long get_sdram_size(void); * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ -#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ /* * Environment Configuration