X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FP1010RDB.h;h=a249fa6ef2fd83d4679230b197bc9fee09f5667e;hb=d56b4b19744c314c26dc77585a7c7a9253d1487d;hp=efdffc4916f1f956a997dab0735da3de2798319f;hpb=8435179271106ec6fe9a9a5679b897755b1db8dd;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index efdffc4..a249fa6 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -11,8 +11,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_P1010 -#define CONFIG_E500 /* BOOKE e500 family */ #include #define CONFIG_NAND_FSL_IFC @@ -20,7 +18,6 @@ #define CONFIG_SPL_MMC_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xD0001000 #define CONFIG_SPL_PAD_TO 0x18000 @@ -46,7 +43,6 @@ #define CONFIG_SPL_SPI_FLASH_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SPL_TEXT_BASE 0xD0001000 #define CONFIG_SPL_PAD_TO 0x18000 @@ -134,13 +130,8 @@ #endif /* High Level Configuration Options */ -#define CONFIG_BOOKE /* BOOKE */ -#define CONFIG_E500 /* BOOKE e500 family */ -#define CONFIG_FSL_IFC /* Enable IFC Support */ -#define CONFIG_FSL_CAAM /* Enable SEC/CAAM */ #define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ -#define CONFIG_PCI /* Enable PCI/PCIE */ #if defined(CONFIG_PCI) #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ @@ -176,9 +167,9 @@ #endif /* controller 2, Slot 2, tgtid 2, Base address 9000 */ -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_PCIE2_NAME "PCIe Slot" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_PCIE2_NAME "mini PCIe Slot" #endif #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 @@ -199,13 +190,9 @@ #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_DOS_PARTITION #endif -#define CONFIG_FSL_LAW /* Use common FSL init code */ #define CONFIG_TSEC_ENET #define CONFIG_ENV_OVERWRITE @@ -234,7 +221,6 @@ #define CONFIG_PANIC_HANG /* do not reset board on panic */ /* DDR Setup */ -#define CONFIG_SYS_FSL_DDR3 #define CONFIG_SYS_DDR_RAW_TIMING #define CONFIG_DDR_SPD #define CONFIG_SYS_SPD_BUS_NUM 1 @@ -316,9 +302,6 @@ extern unsigned long get_sdram_size(void); * IFC Definitions */ /* NOR Flash on IFC */ -#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_NO_FLASH -#endif #define CONFIG_SYS_FLASH_BASE 0xee000000 #define CONFIG_SYS_MAX_FLASH_SECT 256 /* 32M */ @@ -371,7 +354,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_MTD_DEVICE #define CONFIG_MTD_PARTITION -#define CONFIG_CMD_MTDPARTS #define MTDIDS_DEFAULT "nand0=ff800000.flash" #define MTDPARTS_DEFAULT \ "mtdparts=ff800000.flash:2m(uboot-env),1m(dtb),5m(kernel),56m(fs),-(usr)" @@ -382,7 +364,7 @@ extern unsigned long get_sdram_size(void); | CSPR_V) #define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ @@ -392,7 +374,7 @@ extern unsigned long get_sdram_size(void); | CSOR_NAND_PB(32)) /* 32 Pages Per Block */ #define CONFIG_SYS_NAND_BLOCK_SIZE (16 * 1024) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_SYS_NAND_ONFI_DETECTION #define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ @@ -408,7 +390,7 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_CMD_NAND -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ #define CONFIG_SYS_NAND_FTIM0 FTIM0_NAND_TCCST(0x01) | \ FTIM0_NAND_TWP(0x0C) | \ @@ -423,7 +405,7 @@ extern unsigned long get_sdram_size(void); FTIM2_NAND_TWHRE(0x0f) #define CONFIG_SYS_NAND_FTIM3 FTIM3_NAND_TWW(0x04) -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) /* support MT29F16G08ABABAWP 4k-pagesize 2G-bytes NAND */ /* ONFI NAND Flash mode0 Timing Params */ #define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x07)| \ @@ -515,7 +497,6 @@ extern unsigned long get_sdram_size(void); #endif #endif -#define CONFIG_BOARD_EARLY_INIT_F /* Call board_pre_init */ #define CONFIG_BOARD_EARLY_INIT_R #define CONFIG_SYS_INIT_RAM_LOCK @@ -576,8 +557,6 @@ extern unsigned long get_sdram_size(void); #define CONFIG_NS16550_MIN_FUNCTIONS #endif -#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* determine from environment */ - #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} @@ -598,7 +577,7 @@ extern unsigned long get_sdram_size(void); #define I2C_PCA9557_BUS_NUM 0 /* I2C EEPROM */ -#if defined(CONFIG_P1010RDB_PB) +#if defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ID_EEPROM #ifdef CONFIG_ID_EEPROM #define CONFIG_SYS_I2C_EEPROM_NXID @@ -609,7 +588,6 @@ extern unsigned long get_sdram_size(void); #define MAX_NUM_PORTS 9 /* for 128Bytes EEPROM */ #endif /* enable read and write access to EEPROM */ -#define CONFIG_CMD_EEPROM #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 @@ -678,24 +656,18 @@ extern unsigned long get_sdram_size(void); #define CONFIG_SYS_SATA2 CONFIG_SYS_MPC85xx_SATA2_ADDR #define CONFIG_SYS_SATA2_FLAGS FLAGS_DMA -#define CONFIG_CMD_SATA #define CONFIG_LBA48 #endif /* #ifdef CONFIG_FSL_SATA */ -#define CONFIG_MMC #ifdef CONFIG_MMC -#define CONFIG_DOS_PARTITION #define CONFIG_FSL_ESDHC -#define CONFIG_GENERIC_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif #define CONFIG_HAS_FSL_DR_USB #if defined(CONFIG_HAS_FSL_DR_USB) -#define CONFIG_USB_EHCI - -#ifdef CONFIG_USB_EHCI +#ifdef CONFIG_USB_EHCI_HCD #define CONFIG_EHCI_HCD_INIT_AFTER_RESET #define CONFIG_USB_EHCI_FSL #endif @@ -724,10 +696,10 @@ extern unsigned long get_sdram_size(void); #define CONFIG_ENV_SIZE 0x2000 #define CONFIG_ENV_ADDR (CONFIG_SYS_INIT_L2_ADDR + (160 << 10)) #else -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_ENV_SIZE CONFIG_SYS_NAND_BLOCK_SIZE #define CONFIG_ENV_RANGE (3 * CONFIG_ENV_SIZE) /* 3*16=48K for env */ -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_ENV_SIZE (16 * 1024) #define CONFIG_ENV_RANGE (32 * CONFIG_ENV_SIZE) /* new block size 512K */ #endif @@ -750,22 +722,12 @@ extern unsigned long get_sdram_size(void); /* * Command line configuration. */ -#define CONFIG_CMD_DATE -#define CONFIG_CMD_ERRATA -#define CONFIG_CMD_IRQ #define CONFIG_CMD_REGINFO #undef CONFIG_WATCHDOG /* watchdog disabled */ -#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI) \ +#if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ || defined(CONFIG_FSL_SATA) -#define CONFIG_DOS_PARTITION -#endif - -/* Hash command with SHA acceleration supported in hardware */ -#ifdef CONFIG_FSL_CAAM -#define CONFIG_CMD_HASH -#define CONFIG_SHA_HW_ACCEL #endif /* @@ -817,8 +779,6 @@ extern unsigned long get_sdram_size(void); #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ "netdev=eth0\0" \ @@ -848,7 +808,7 @@ extern unsigned long get_sdram_size(void); "bootm $loadaddr $ramdiskaddr $fdtaddr\0" \ CONFIG_BOOTMODE -#if defined(CONFIG_P1010RDB_PA) +#if defined(CONFIG_TARGET_P1010RDB_PA) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 f1; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00009 0; reset\0" \ @@ -857,7 +817,7 @@ extern unsigned long get_sdram_size(void); "boot_nand=i2c dev 0; i2c mw 18 1 f9; i2c mw 18 3 f0;" \ "mw.b ffb00011 0; mw.b ffb00017 1; reset\0" -#elif defined(CONFIG_P1010RDB_PB) +#elif defined(CONFIG_TARGET_P1010RDB_PB) #define CONFIG_BOOTMODE \ "boot_bank0=i2c dev 0; i2c mw 18 1 fe; i2c mw 18 3 0;" \ "i2c mw 19 1 2; i2c mw 19 3 e1; reset\0" \