X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FOCRTC.h;h=aa9d1ba735a028d73b9adbe9ca41f62f4e212d25;hb=4e3ccd26925e5ada78dd89779838f052dffe3e67;hp=c88d882e0bf4ad4ca3d09067d8632e329df0d967;hpb=c837dcb1a316745092567bfe4fb266d0941884ff;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/OCRTC.h b/include/configs/OCRTC.h
index c88d882..aa9d1ba 100644
--- a/include/configs/OCRTC.h
+++ b/include/configs/OCRTC.h
@@ -52,6 +52,7 @@
 
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
+#define CONFIG_LXT971_NO_SLEEP  1       /* disable sleep mode in LXT971 */
 
 #define CONFIG_COMMANDS	      ( CONFIG_CMD_DFL	| \
 				CFG_CMD_PCI	| \
@@ -121,7 +122,7 @@
 
 #define CONFIG_PCI_SCAN_SHOW		/* print pci devices @ startup	*/
 
-#define CONFIG_PCI_BOOTDELAY	0	/* enable pci bootdelay variable*/
+#define CONFIG_PCI_BOOTDELAY	1	/* enable pci bootdelay variable*/
 
 #define CFG_PCI_SUBSYS_VENDORID 0x12FE	/* PCI Vendor ID: esd gmbh	*/
 #define CFG_PCI_SUBSYS_DEVICEID 0x0410	/* PCI Device ID: OCRTC		*/
@@ -212,7 +213,7 @@
 /*-----------------------------------------------------------------------
  * Cache Configuration
  */
-#define CFG_DCACHE_SIZE		8192	/* For IBM 405 CPUs			*/
+#define CFG_DCACHE_SIZE		8192	/* For AMCC 405 CPUs			*/
 #define CFG_CACHELINE_SIZE	32	/* ...			*/
 #if (CONFIG_COMMANDS & CFG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
@@ -270,7 +271,7 @@
 #define CFG_EBC_PB7CR		0xF509A000  /* BAS=0xF50,BS=16MB,BU=R/W,BW=16bit*/
 
 
-#define CFG_ETHERNET_MAC_ADDR	0x00000000	/* Pass Ethernet MAC to VxWorks */
+#define CFG_VXWORKS_MAC_PTR	0x00000000	/* Pass Ethernet MAC to VxWorks */
 
 /*-----------------------------------------------------------------------
  * Definitions for initial stack pointer and data area (in DPRAM)