X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FNETTA.h;h=e2e8803394e7d1ea1a0878561fb7305384ceacf4;hb=e18a1061a8630cb67995fdf99afd3fb50d1b187d;hp=76e9cb4c1e0aacb71f98c38e1837bf5eac518e5d;hpb=04a85b3b36fdbaaac5fa95d61f59f481bbcf7520;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 76e9cb4..e2e8803 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -65,8 +65,8 @@
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
 	"tftpboot; " 								\
-	"setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " 	\
-	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " 	\
+	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
+	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
 	"bootm"
 
 #define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
@@ -108,24 +108,31 @@
 
 /* POST support */
 #define CONFIG_POST		(CFG_POST_MEMORY   | \
+				 CFG_POST_CODEC	   | \
 				 CFG_POST_DSP	   )
 
-#define CONFIG_COMMANDS       ( CONFIG_CMD_DFL	| \
-				CFG_CMD_NAND	| \
-				CFG_CMD_DHCP	| \
-				CFG_CMD_PING  	| \
-				CFG_CMD_MII 	| \
-				CFG_CMD_PCMCIA	| CFG_CMD_IDE | CFG_CMD_FAT | \
-				CFG_CMD_DIAG    | \
-				CFG_CMD_CDP	  \
-				)
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_CDP
+#define CONFIG_CMD_DHCP
+#define CONFIG_CMD_DIAG
+#define CONFIG_CMD_FAT
+#define CONFIG_CMD_IDE
+#define CONFIG_CMD_JFFS2
+#define CONFIG_CMD_MII
+#define CONFIG_CMD_NAND
+#define CONFIG_CMD_NFS
+#define CONFIG_CMD_PCMCIA
+#define CONFIG_CMD_PING
+
 
 #define CONFIG_BOARD_EARLY_INIT_F	1
 #define CONFIG_MISC_INIT_R
 
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
 /*
  * Miscellaneous configurable options
  */
@@ -135,7 +142,7 @@
 #define CFG_HUSH_PARSER	1
 #define CFG_PROMPT_HUSH_PS2	"> "
 
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define	CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define	CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
@@ -218,7 +225,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
 #endif
 
@@ -338,18 +345,20 @@
  *-----------------------------------------------------------------------
  * Set clock output, timebase and RTC source and divider,
  * power management and some other internal clocks
+ *
+ * Note: When TBS == 0 the timebase is independent of current cpu clock.
  */
 
 #define SCCR_MASK	SCCR_EBDF11
 #if MPC8XX_HZ > 66666666
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL001 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00 | SCCR_EBDF01)
 #else
-#define CFG_SCCR	(SCCR_TBS     | \
+#define CFG_SCCR	(/* SCCR_TBS	| */ SCCR_CRQEN | \
 			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
-			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
+			 SCCR_DFNL111 | SCCR_DFNH000  | SCCR_DFLCD000 | \
 			 SCCR_DFALCD00)
 #endif
 
@@ -602,11 +611,13 @@
 /****************************************************************/
 
 /* NAND */
+#define CFG_NAND_LEGACY
 #define CFG_NAND_BASE			NAND_BASE
-#define CONFIG_MTD_NAND_ECC_JFFS2
+#define CONFIG_MTD_NAND_VERIFY_WRITE
+#define CONFIG_MTD_NAND_UNSAFE
 
 #define CFG_MAX_NAND_DEVICE		1
-#define NAND_NO_RB
+/* #define NAND_NO_RB */
 
 #define SECTORSIZE		512
 #define ADDR_COLUMN		1
@@ -676,6 +687,32 @@
 #define READ_NAND(adr) \
 	((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr)))
 
+#define CONFIG_JFFS2_NAND	1			/* jffs2 on nand support */
+#define NAND_CACHE_PAGES	16			/* size of nand cache in 512 bytes pages */
+
+/*
+ * JFFS2 partitions
+ *
+ */
+/* No command line, one static partition, whole device */
+#undef CONFIG_JFFS2_CMDLINE
+#define CONFIG_JFFS2_DEV		"nand0"
+#define CONFIG_JFFS2_PART_SIZE		0x00100000
+#define CONFIG_JFFS2_PART_OFFSET	0x00200000
+
+/* mtdparts command line support */
+/* Note: fake mtd_id used, no linux mtd map file */
+/*
+#define CONFIG_JFFS2_CMDLINE
+#define MTDIDS_DEFAULT		"nand0=netta-nand"
+#define MTDPARTS_DEFAULT	"mtdparts=netta-nand:1m@2m(jffs2)"
+*/
+
+/*****************************************************************************/
+
+#define CFG_DIRECT_FLASH_TFTP
+#define CFG_DIRECT_NAND_TFTP
+
 /*****************************************************************************/
 
 #if 1
@@ -742,4 +779,12 @@
 
 /*************************************************************************************************/
 
+#define CONFIG_CRC32_VERIFY	1
+
+/*************************************************************************************************/
+
+#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1
+
+/*************************************************************************************************/
+
 #endif	/* __CONFIG_H */