X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FNETTA.h;h=56c76d3258c61f4574b0cc6533f20ca590a468b6;hb=29f8f58ff40c67f7f2e11afd1715173094e52ac2;hp=19743c04e87d12106d1da82c073bba41cce0b6fb;hpb=375c2c9e57ea5b8d678475379378f4774aa9cb88;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h
index 19743c0..56c76d3 100644
--- a/include/configs/NETTA.h
+++ b/include/configs/NETTA.h
@@ -60,11 +60,11 @@
 
 #undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */
 
-#define CONFIG_PREBOOT	"echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo"
+#define CONFIG_PREBOOT	"echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo"
 
 #undef	CONFIG_BOOTARGS
 #define CONFIG_BOOTCOMMAND							\
-	"tftpboot; " 								\
+	"tftpboot; "								\
 	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
 	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;"	\
 	"bootm"
@@ -93,23 +93,24 @@
 
 #define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/
 
-#define	CONFIG_NET_MULTI	1 	/* the only way to get the FEC in */
+#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
 #define	FEC_ENET		1	/* eth.c needs it that way... */
 #undef  CFG_DISCOVER_PHY		/* do not discover phys */
 #define CONFIG_MII		1
+#define CONFIG_MII_INIT		1
 #define CONFIG_RMII		1	/* use RMII interface */
 
 #if defined(CONFIG_NETTA_ISDN)
 #define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		1   	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY		1	/* phy address of FEC1 */
 #define CONFIG_FEC1_PHY_NORXERR 1
 #undef  CONFIG_ETHER_ON_FEC2
 #else
 #define CONFIG_ETHER_ON_FEC1	1
-#define CONFIG_FEC1_PHY		8  	/* phy address of FEC1 */
+#define CONFIG_FEC1_PHY		8	/* phy address of FEC1 */
 #define CONFIG_FEC1_PHY_NORXERR 1
 #define CONFIG_ETHER_ON_FEC2	1
-#define CONFIG_FEC2_PHY		1   	/* phy address of FEC2 */
+#define CONFIG_FEC2_PHY		1	/* phy address of FEC2 */
 #define CONFIG_FEC2_PHY_NORXERR 1
 #endif
 
@@ -295,27 +296,27 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 50000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 25000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (2 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (3 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 40000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 75000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (15 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 10MHz
 #endif
@@ -325,19 +326,19 @@
 #if MPC8XX_HZ == 120000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (12 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ == 100000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  80000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (0 << PLPRCR_S_SHIFT) | (8 << PLPRCR_MFI_SHIFT) | (4 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #elif MPC8XX_HZ ==  50000000
 #define CFG_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
 			 (1 << PLPRCR_S_SHIFT) | (6 << PLPRCR_MFI_SHIFT) | (2 << PLPRCR_PDF_SHIFT) | \
-		 	 PLPRCR_TEXPS)
+			 PLPRCR_TEXPS)
 #else
 #error unsupported CPU freq for XIN = 50MHz
 #endif
@@ -632,7 +633,7 @@
 #define ADDR_COLUMN		1
 #define ADDR_PAGE		2
 #define ADDR_COLUMN_PAGE	3
-#define NAND_ChipID_UNKNOWN 	0x00
+#define NAND_ChipID_UNKNOWN	0x00
 #define NAND_MAX_FLOORS		1
 #define NAND_MAX_CHIPS		1