X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FNETTA.h;h=19743c04e87d12106d1da82c073bba41cce0b6fb;hb=7be044e4ea644b0ef1c486dadc1a4c2665b4374d;hp=1bcd88d208a3ea3027f9b2dc0a4339c23e4781c6;hpb=8f79e4c2da54cea11bb576870059fc1ba8847ccb;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 1bcd88d..19743c0 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -77,7 +77,16 @@ #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_NISDOMAIN + #undef CONFIG_MAC_PARTITION #undef CONFIG_DOS_PARTITION @@ -111,26 +120,28 @@ CFG_POST_CODEC | \ CFG_POST_DSP ) -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_CDP | \ - CFG_CMD_DHCP | \ - CFG_CMD_DIAG | \ - CFG_CMD_FAT | \ - CFG_CMD_IDE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_MII | \ - CFG_CMD_NAND | \ - CFG_CMD_NFS | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_PING | \ - 0) + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CDP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_FAT +#define CONFIG_CMD_IDE +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCMCIA +#define CONFIG_CMD_PING + #define CONFIG_BOARD_EARLY_INIT_F 1 #define CONFIG_MISC_INIT_R -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - /* * Miscellaneous configurable options */ @@ -140,7 +151,7 @@ #define CFG_HUSH_PARSER 1 #define CFG_PROMPT_HUSH_PS2 "> " -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -223,7 +234,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif @@ -609,6 +620,7 @@ /****************************************************************/ /* NAND */ +#define CFG_NAND_LEGACY #define CFG_NAND_BASE NAND_BASE #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_MTD_NAND_UNSAFE