X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FNC650.h;h=84c6e9b6179c7539c4405b7e98e876abea416a08;hb=29f8f58ff40c67f7f2e11afd1715173094e52ac2;hp=48bea694df302cd3fed16b7a77af90952e6391b4;hpb=cce625e557416d06aeddaab0967b3119748cd21e;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/NC650.h b/include/configs/NC650.h index 48bea69..84c6e9b 100644 --- a/include/configs/NC650.h +++ b/include/configs/NC650.h @@ -1,5 +1,6 @@ /* - * (C) Copyright 2004 + * (C) Copyright 2006, 2007 Detlev Zundel, dzu@denx.de + * (C) Copyright 2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -64,22 +65,36 @@ #define CFG_MEASURE_CPUCLK #define CFG_8XX_XIN CONFIG_8xx_OSCLK -#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ +#define CONFIG_AUTOBOOT_KEYED +#define CONFIG_AUTOBOOT_PROMPT \ + "\nEnter password - autoboot in %d seconds...\n", bootdelay +#define CONFIG_AUTOBOOT_DELAY_STR "ids" +#define CONFIG_BOOT_RETRY_TIME 900 +#define CONFIG_BOOT_RETRY_MIN 30 -#define CONFIG_PREBOOT "echo;echo Type \"run flash_nfs\" to mount root filesystem over NFS;echo" +#define CONFIG_PREBOOT "echo;echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;echo" #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ - "bootp;" \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off;" \ + "bootp;" \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off;" \ "bootm" -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_WATCHDOG /* watchdog enabled */ #undef CONFIG_STATUS_LED /* Status LED disabled */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ #define FEC_ENET @@ -96,45 +111,60 @@ /* * Software (bit-bang) I2C driver configuration */ -#define SCL 0x10000000 /* PA 3 */ -#define SDA 0x40000000 /* PA 1 */ +#if defined(CONFIG_IDS852_REV1) + +#define SCL 0x1000 /* PA 3 */ +#define SDA 0x2000 /* PA 2 */ + +#define __I2C_DIR immr->im_ioport.iop_padir +#define __I2C_DAT immr->im_ioport.iop_padat +#define __I2C_PAR immr->im_ioport.iop_papar + +#elif defined(CONFIG_IDS852_REV2) -#define PAR immr->im_ioport.iop_papar -#define DIR immr->im_ioport.iop_padir -#define DAT immr->im_ioport.iop_padat +#define SCL 0x0002 /* PB 30 */ +#define SDA 0x0001 /* PB 31 */ -#define I2C_INIT {PAR &= ~(SCL | SDA); DIR |= SCL;} -#define I2C_ACTIVE (DIR |= SDA) -#define I2C_TRISTATE (DIR &= ~SDA) -#define I2C_READ ((DAT & SDA) != 0) -#define I2C_SDA(bit) if (bit) DAT |= SDA; \ - else DAT &= ~SDA -#define I2C_SCL(bit) if (bit) DAT |= SCL; \ - else DAT &= ~SCL -#define I2C_DELAY udelay(50) /* 1/4 I2C clock duration */ +#define __I2C_PAR immr->im_cpm.cp_pbpar +#define __I2C_DIR immr->im_cpm.cp_pbdir +#define __I2C_DAT immr->im_cpm.cp_pbdat -#define CFG_I2C_EEPROM_ADDR 0x50 -#define CFG_I2C_EEPROM_ADDR_LEN 1 -#define CFG_EEPROM_PAGE_WRITE_BITS 4 /* 16 bytes page write mode */ +#endif + +#define I2C_INIT { __I2C_PAR &= ~(SDA|SCL); \ + __I2C_DIR |= (SDA|SCL); } +#define I2C_READ ((__I2C_DAT & SDA) ? 1 : 0) +#define I2C_SDA(x) { if (x) __I2C_DAT |= SDA; else __I2C_DAT &= ~SDA; } +#define I2C_SCL(x) { if (x) __I2C_DAT |= SCL; else __I2C_DAT &= ~SCL; } +#define I2C_DELAY { udelay(5); } +#define I2C_ACTIVE { __I2C_DIR |= SDA; } +#define I2C_TRISTATE { __I2C_DIR &= ~SDA; } + +#define CONFIG_RTC_PCF8563 +#define CFG_I2C_RTC_ADDR 0x51 -#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_ASKENV | \ - CFG_CMD_DHCP | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_DATE ) +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -146,7 +176,7 @@ #define CFG_MEMTEST_START 0x0100000 /* memtest works on */ #define CFG_MEMTEST_END 0x0400000 /* 1 ... 4 MB in DRAM */ -#define CFG_LOAD_ADDR 0x00100000 +#define CFG_LOAD_ADDR 0x00100000 #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -212,10 +242,16 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ #endif +/* + * NAND flash support + */ +#define CFG_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 + /*----------------------------------------------------------------------- * SYPCR - System Protection Control 11-9 * SYPCR can only be written once after reset! @@ -287,6 +323,19 @@ #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_8 | BR_V) /* + * BR2 and OR2 (NAND Flash) - addressed through UPMB on rev 1 + * rev2 only uses the chipselect + */ +#define CFG_NAND_BASE 0x50000000 +#define CFG_NAND_SIZE 0x04000000 + +#define CFG_OR_TIMING_NAND (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_15_CLK | OR_EHTR | OR_TRLX) + +#define CFG_BR2_PRELIM ((CFG_NAND_BASE & BR_BA_MSK) | BR_PS_8 | BR_MS_UPMB | BR_V ) +#define CFG_OR2_PRELIM (((-CFG_NAND_SIZE) & OR_AM_MSK) | OR_BI ) + +/* * BR3 and OR3 (SDRAM) */ #define SDRAM_BASE3_PRELIM 0x00000000 /* SDRAM bank */ @@ -301,6 +350,41 @@ #define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V) /* + * BR4 and OR4 (CPLD) + */ +#define CFG_CPLD_BASE 0x80000000 /* CPLD */ +#define CFG_CPLD_SIZE 0x10000 /* only 16 used */ + +#define CFG_OR_TIMING_CPLD (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_1_CLK) + +#define CFG_BR4_PRELIM ((CFG_CPLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR4_PRELIM (((-CFG_CPLD_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_CPLD) + +/* + * BR5 and OR5 (SRAM) + */ +#define CFG_SRAM_BASE 0x60000000 +#define CFG_SRAM_SIZE 0x00080000 + +#define CFG_OR_TIMING_SRAM (OR_CSNT_SAM | OR_ACS_DIV1 | OR_BI | \ + OR_SCY_15_CLK | OR_EHTR | OR_TRLX) + +#define CFG_BR5_PRELIM ((CFG_SRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V ) +#define CFG_OR5_PRELIM (((-CFG_SRAM_SIZE) & OR_AM_MSK) | CFG_OR_TIMING_SRAM) + +#if defined(CONFIG_CP850) +/* + * BR6 and OR6 (DPRAM) - only on CP850 + */ +#define CFG_OR6_PRELIM 0xffff8170 +#define CFG_BR6_PRELIM 0xa0000401 +#define DPRAM_BASE_ADDR 0xa0000000 + +#define CONFIG_MISC_INIT_R 1 +#endif + +/* * 4096 Rows from SDRAM example configuration * 1000 factor s -> ms * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration @@ -336,6 +420,12 @@ MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) /* + * MBMR settings for NAND flash + */ + +#define CFG_MBMR_NAND ( MBMR_WLFB_5X ) + +/* * Internal Definitions * * Boot Flags @@ -343,5 +433,26 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_JFFS2_NAND 1 /* jffs2 on nand support */ +#define NAND_CACHE_PAGES 16 /* size of nand cache in 512 bytes pages */ + +/* + * JFFS2 partitions + */ + +/* No command line, one static partition */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nand0" +#define CONFIG_JFFS2_PART_SIZE 0x00400000 +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +#define CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nor0=nc650-0,nand0=nc650-nand" + +#define MTDPARTS_DEFAULT "mtdparts=nc650-0:1m(kernel1),1m(kernel2)," \ + "4m(cramfs1),1m(cramfs2)," \ + "256k(u-boot),128k(env);" \ + "nc650-nand:4m(jffs1),28m(jffs2)" #endif /* __CONFIG_H */