X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8641HPCN.h;h=9009e3c48733811230fd7a9c4637915f389ffc46;hb=37a3bda0c9c8a2ffbf7e2a9e121177a3385a0626;hp=d8042fb764a4a24925cede9b3bade14f782ed1bb;hpb=da72af8d727e74093e5fcb3e8599eb8d0df7a749;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index d8042fb..9009e3c 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -1,5 +1,5 @@ /* - * Copyright 2006 Freescale Semiconductor. + * Copyright 2006, 2010 Freescale Semiconductor. * * Srikanth Srinivasan (srikanth.srinivasan@freescale.com) * @@ -37,11 +37,16 @@ #define CONFIG_MPC8641 1 /* MPC8641 specific */ #define CONFIG_MPC8641HPCN 1 /* MPC8641HPCN board specific */ #define CONFIG_MP 1 /* support multiple processors */ -#define CONFIG_NUM_CPUS 2 /* Number of CPUs in the system */ #define CONFIG_LINUX_RESET_VEC 0x100 /* Reset vector used by Linux */ /*#define CONFIG_PHYS_64BIT 1*/ /* Place devices in 36-bit space */ #define CONFIG_ADDR_MAP 1 /* Use addr map */ +/* + * default CCSRBAR is at 0xff700000 + * assume U-Boot is less than 0.5MB + */ +#define CONFIG_SYS_TEXT_BASE 0xeff00000 + #ifdef RUN_DIAG #define CONFIG_SYS_DIAG_ADDR CONFIG_SYS_FLASH_BASE #endif @@ -59,8 +64,8 @@ #ifndef CONFIG_RIO /* RIO/PCI are mutually exclusive */ #define CONFIG_PCI 1 /* Enable PCI/PCIE */ -#define CONFIG_PCI1 1 /* PCIE controler 1 (ULI bridge) */ -#define CONFIG_PCI2 1 /* PCIE controler 2 (slot) */ +#define CONFIG_PCIE1 1 /* PCIE controler 1 (ULI bridge) */ +#define CONFIG_PCIE2 1 /* PCIE controler 2 (slot) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #endif @@ -69,6 +74,7 @@ #define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE +#define CONFIG_BAT_RW 1 /* Use common BAT rw code */ #define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_SYS_NUM_ADDR_MAP 8 /* Number of addr map slots = 8 dbats */ @@ -123,8 +129,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR_PHYS_LOW #endif -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) +#define CONFIG_HWCONFIG /* use hwconfig to control memory interleaving */ /* * DDR Setup @@ -142,8 +147,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM -#define MPC86xx_DDR_SDRAM_CLK_CNTL - #define CONFIG_NUM_DDR_CONTROLLERS 2 #define CONFIG_DIMM_SLOTS_PER_CTLR 2 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) @@ -224,6 +227,8 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define PIXIS_VCFGEN0 0x12 /* VELA Config Enable 0 */ #define PIXIS_VCFGEN1 0x13 /* VELA Config Enable 1 */ #define PIXIS_VBOOT 0x16 /* VELA VBOOT Register */ +#define PIXIS_VBOOT_FMAP 0x80 /* VBOOT - CFG_FLASHMAP */ +#define PIXIS_VBOOT_FBANK 0x40 /* VBOOT - CFG_FLASHBANK */ #define PIXIS_VSPEED0 0x17 /* VELA VSpeed 0 */ #define PIXIS_VSPEED1 0x18 /* VELA VSpeed 1 */ #define PIXIS_VCLKH 0x19 /* VELA VCLKH register */ @@ -240,7 +245,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_SYS_MONITOR_BASE_EARLY 0xfff00000 /* early monitor loc */ #define CONFIG_FLASH_CFI_DRIVER @@ -277,7 +282,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -302,10 +306,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 - -#define CONFIG_SYS_64BIT_VSPRINTF 1 -#define CONFIG_SYS_64BIT_STRTOUL 1 - /* * I2C */ @@ -333,47 +333,43 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Addresses are mapped 1-1. */ -#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCI1_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCI1_MEM_PHYS 0x0000000c00000000ULL +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0x0000000c00000000ULL #else -#define CONFIG_SYS_PCI1_MEM_BUS CONFIG_SYS_PCI1_MEM_VIRT -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_BUS CONFIG_SYS_PCIE1_MEM_VIRT +#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_VIRT #endif -#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCI1_IO_PHYS (CONFIG_SYS_PCI1_IO_VIRT \ +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_PHYS (CONFIG_SYS_PCIE1_IO_VIRT \ | CONFIG_SYS_PHYS_ADDR_HIGH) -#define CONFIG_SYS_PCI1_IO_SIZE 0x00010000 /* 64K */ - -/* For RTL8139 */ -#define KSEG1ADDR(x) ({u32 _x=le32_to_cpu(*(u32 *)(x)); (&_x);}) -#define _IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64K */ #ifdef CONFIG_PHYS_64BIT /* - * Use the same PCI bus address on PCI1 and PCI2 if we have PHYS_64BIT. + * Use the same PCI bus address on PCIE1 and PCIE2 if we have PHYS_64BIT. * This will increase the amount of PCI address space available for * for mapping RAM. */ -#define CONFIG_SYS_PCI2_MEM_BUS CONFIG_SYS_PCI1_MEM_BUS +#define CONFIG_SYS_PCIE2_MEM_BUS CONFIG_SYS_PCIE1_MEM_BUS #else -#define CONFIG_SYS_PCI2_MEM_BUS (CONFIG_SYS_PCI1_MEM_BUS \ - + CONFIG_SYS_PCI1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_BUS (CONFIG_SYS_PCIE1_MEM_BUS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) #endif -#define CONFIG_SYS_PCI2_MEM_VIRT (CONFIG_SYS_PCI1_MEM_VIRT \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_PHYS (CONFIG_SYS_PCI1_MEM_PHYS \ - + CONFIG_SYS_PCI1_MEM_SIZE) -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 -#define CONFIG_SYS_PCI2_IO_VIRT (CONFIG_SYS_PCI1_IO_VIRT \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_PHYS (CONFIG_SYS_PCI1_IO_PHYS \ - + CONFIG_SYS_PCI1_IO_SIZE) -#define CONFIG_SYS_PCI2_IO_SIZE CONFIG_SYS_PCI1_IO_SIZE +#define CONFIG_SYS_PCIE2_MEM_VIRT (CONFIG_SYS_PCIE1_MEM_VIRT \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_PHYS (CONFIG_SYS_PCIE1_MEM_PHYS \ + + CONFIG_SYS_PCIE1_MEM_SIZE) +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_VIRT (CONFIG_SYS_PCIE1_IO_VIRT \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_PHYS (CONFIG_SYS_PCIE1_IO_PHYS \ + + CONFIG_SYS_PCIE1_IO_SIZE) +#define CONFIG_SYS_PCIE2_IO_SIZE CONFIG_SYS_PCIE1_IO_SIZE #if defined(CONFIG_PCI) @@ -395,17 +391,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_PCI_OHCI 1 #define CONFIG_USB_OHCI_NEW 1 #define CONFIG_USB_KEYBOARD 1 -#define CONFIG_SYS_DEVICE_DEREGISTER +#define CONFIG_SYS_STDIO_DEREGISTER #define CONFIG_SYS_USB_EVENT_POLL 1 #define CONFIG_SYS_USB_OHCI_SLOT_NAME "ohci_pci" #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 15 #define CONFIG_SYS_OHCI_SWAP_REG_ACCESS 1 /*PCIE video card used*/ -#define VIDEO_IO_OFFSET CONFIG_SYS_PCI2_IO_VIRT +#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE2_IO_VIRT /*PCI video card used*/ -/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCI1_IO_VIRT*/ +/*#define VIDEO_IO_OFFSET CONFIG_SYS_PCIE1_IO_VIRT*/ /* video */ #define CONFIG_VIDEO @@ -418,7 +414,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_ATI_RADEON_FB #define CONFIG_VIDEO_LOGO /*#define CONFIG_CONSOLE_CURSOR*/ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCI2_IO_VIRT +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS CONFIG_SYS_PCIE2_IO_VIRT #endif #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -434,8 +430,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE #endif -#define CONFIG_MPC86XX_PCI2 - #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) @@ -491,9 +485,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * BAT0 DDR */ #define CONFIG_SYS_DBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) -#define CONFIG_SYS_DBAT0U (BATU_BL_2G | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE ) -#define CONFIG_SYS_IBAT0U CONFIG_SYS_DBAT0U +#define CONFIG_SYS_IBAT0L (BATL_PP_RW | BATL_MEMCOHERENCE) /* * BAT1 LBC (PIXIS/CF) @@ -508,17 +500,17 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_IBAT1U CONFIG_SYS_DBAT1U /* if CONFIG_PCI: - * BAT2 PCI1 and PCI1 MEM + * BAT2 PCIE1 and PCIE1 MEM * if CONFIG_RIO * BAT2 Rapidio Memory */ #ifdef CONFIG_PCI -#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_DBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCI1_MEM_VIRT | BATU_BL_1G \ +#define CONFIG_SYS_DBAT2U (CONFIG_SYS_PCIE1_MEM_VIRT | BATU_BL_1G \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_MEM_PHYS) \ +#define CONFIG_SYS_IBAT2L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_MEM_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT2U CONFIG_SYS_DBAT2U #else /* CONFIG_RIO */ @@ -567,14 +559,14 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #endif /* - * BAT4 PCI1_IO and PCI2_IO + * BAT4 PCIE1_IO and PCIE2_IO */ -#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_DBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCI1_IO_VIRT | BATU_BL_128K \ +#define CONFIG_SYS_DBAT4U (CONFIG_SYS_PCIE1_IO_VIRT | BATU_BL_128K \ | BATU_VS | BATU_VP) -#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCI1_IO_PHYS) \ +#define CONFIG_SYS_IBAT4L (BAT_PHYS_ADDR(CONFIG_SYS_PCIE1_IO_PHYS) \ | BATL_PP_RW | BATL_CACHEINHIBIT) #define CONFIG_SYS_IBAT4U CONFIG_SYS_DBAT4U @@ -601,7 +593,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); /* Map the last 1M of flash where we're running from reset */ #define CONFIG_SYS_DBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT6U_EARLY (TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) +#define CONFIG_SYS_DBAT6U_EARLY (CONFIG_SYS_TEXT_BASE | BATU_BL_1M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT6L_EARLY (CONFIG_SYS_MONITOR_BASE_EARLY | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U_EARLY CONFIG_SYS_DBAT6U_EARLY @@ -689,14 +681,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ @@ -742,11 +726,11 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ "consoledev=ttyS0\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=your.ramdisk.u-boot\0" \