X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8572DS.h;h=e3952f423bfb4aa468abcbf4288a08e9eb64cf84;hb=2b12f6cfe6239d8b6b8c5e7b0c5b5851f7bc489a;hp=c04b3a2af2cb2b6d083f684fe69ff57b5666faef;hpb=844fb498cc978608ec88bdf29913c0d46c85bfff;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index c04b3a2..e3952f4 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2007-2008,2010-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -22,14 +21,12 @@ #endif /* High Level Configuration Options */ -#define CONFIG_MP 1 /* support multiple processors */ #define CONFIG_PCIE1 1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 1 /* PCIE controller 2 (slot 2) */ #define CONFIG_PCIE3 1 /* PCIE controller 3 (ULI bridge) */ #define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ #define CONFIG_ENV_OVERWRITE @@ -75,7 +72,6 @@ /* DDR Setup */ #define CONFIG_VERY_BIG_RAM -#undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD @@ -174,8 +170,6 @@ #undef CONFIG_SYS_RAMBOOT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_SYS_FLASH_AMD_CHECK_DQ7 @@ -466,14 +460,12 @@ #define CONFIG_SYS_SCSI_MAX_SCSI_ID 4 #define CONFIG_SYS_SCSI_MAX_LUN 1 #define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * CONFIG_SYS_SCSI_MAX_LUN) -#define CONFIG_SYS_SCSI_MAXDEVICE CONFIG_SYS_SCSI_MAX_DEVICE #endif /* SCSI */ #endif /* CONFIG_PCI */ #if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1"