X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8569MDS.h;h=acd3276e9826e30e14767c9f6b7be0ac7ea20907;hb=bb367b95f9204115bd6eac82e839b5590e6da4eb;hp=177d5d5362c67d76016988055e529abc9f767acc;hpb=a6da8b8195f47a70106f743948f2729d94157b32;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 177d5d5..acd3276 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,5 +1,5 @@ /* - * Copyright (C) 2009-2010 Freescale Semiconductor, Inc. + * Copyright 2009-2011 Freescale Semiconductor, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -35,6 +35,9 @@ #define CONFIG_FSL_ELBC 1 /* Has Enhance localbus controller */ +#define CONFIG_SYS_SRIO +#define CONFIG_SRIO1 /* SRIO port 1 */ + #define CONFIG_PCI 1 /* Disable PCI/PCIE */ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ @@ -69,6 +72,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_TEXT_BASE_SPL 0xfff00000 #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE_SPL /* start of monitor */ #else +#define CONFIG_SYS_LDSCRIPT $(TOPDIR)/$(CPUDIR)/u-boot-nand.lds #define CONFIG_SYS_TEXT_BASE 0xf8f82000 #endif #endif @@ -101,20 +105,11 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_L2_SIZE (512 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) -/* - * Base addresses -- Note these are effective addresses where the - * actual resources get mapped (not physical addresses) - */ -#define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ -#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR - /* physical addr of CCSRBAR */ -#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR - /* PQII uses CONFIG_SYS_IMMR */ - -#if defined(CONFIG_RAMBOOT_NAND) && !defined(CONFIG_NAND_SPL) -#define CONFIG_SYS_CCSRBAR_DEFAULT CONFIG_SYS_CCSRBAR -#else -#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ +#define CONFIG_SYS_CCSRBAR 0xe0000000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +#if defined(CONFIG_NAND_SPL) +#define CONFIG_SYS_CCSR_DO_NOT_RELOCATE #endif /* DDR Setup */ @@ -135,8 +130,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) /* I2C addresses of SPD EEPROMs */ -#define SPD_EEPROM_ADDRESS1 0x51 /* CTLR 0 DIMM 0 */ -#define SPD_EEPROM_ADDRESS2 0x52 /* CTLR 1 DIMM 0 */ +#define SPD_EEPROM_ADDRESS 0x51 /* CTLR 0 DIMM 0 */ /* These are used when DDR doesn't use SPD. */ #define CONFIG_SYS_SDRAM_SIZE 1024 /* DDR is 1024MB */ @@ -237,12 +231,12 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) -#define CONFIG_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ +#define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ | (2< " #endif /* pass open firmware flat tree */ @@ -345,6 +337,7 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory Addresses are mapped 1-1. I/O is mapped from 0 */ +#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 @@ -354,9 +347,10 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ -#define CONFIG_SYS_SRIO_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_BUS 0xc0000000 -#define CONFIG_SYS_SRIO_MEM_PHYS 0xc0000000 +#define CONFIG_SYS_SRIO1_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_BUS 0xC0000000 +#define CONFIG_SYS_SRIO1_MEM_PHYS CONFIG_SYS_SRIO1_MEM_BUS +#define CONFIG_SYS_SRIO1_MEM_SIZE 0x20000000 /* 512M */ #ifdef CONFIG_QE /* @@ -380,13 +374,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC1_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC1_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 7 -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC1_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC1_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC1_PHY_ADDR 8 /* 0x8 for RMII */ -#define CONFIG_SYS_UEC1_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH1 */ @@ -401,13 +395,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC2_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC2_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 1 -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC2_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC2_TX_CLK QE_CLK16 /* CLK 16 for RMII */ #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC2_PHY_ADDR 0x9 /* 0x9 for RMII */ -#define CONFIG_SYS_UEC2_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH2 */ @@ -422,13 +416,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC3_TX_CLK QE_CLK12 #define CONFIG_SYS_UEC3_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 2 -#define CONFIG_SYS_UEC3_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC3_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC3_TX_CLK QE_CLK16 /* CLK_16 for RMII */ #define CONFIG_SYS_UEC3_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC3_PHY_ADDR 0xA /* 0xA for RMII */ -#define CONFIG_SYS_UEC3_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC3_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC3_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH3 */ @@ -443,13 +437,13 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC4_TX_CLK QE_CLK17 #define CONFIG_SYS_UEC4_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 3 -#define CONFIG_SYS_UEC4_INTERFACE_TYPE RGMII_ID +#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RGMII_ID #define CONFIG_SYS_UEC4_INTERFACE_SPEED 1000 #elif defined(CONFIG_SYS_UCC_RMII_MODE) #define CONFIG_SYS_UEC4_TX_CLK QE_CLK16 /* CLK16 for RMII */ #define CONFIG_SYS_UEC4_ETH_TYPE FAST_ETH #define CONFIG_SYS_UEC4_PHY_ADDR 0xB /* 0xB for RMII */ -#define CONFIG_SYS_UEC4_INTERFACE_TYPE RMII +#define CONFIG_SYS_UEC4_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII #define CONFIG_SYS_UEC4_INTERFACE_SPEED 100 #endif /* CONFIG_SYS_UCC_RGMII_MODE */ #endif /* CONFIG_UEC_ETH4 */ @@ -463,7 +457,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC6_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC6_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC6_PHY_ADDR 4 -#define CONFIG_SYS_UEC6_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC6_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII #define CONFIG_SYS_UEC6_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH6 */ @@ -476,7 +470,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_UEC8_TX_CLK QE_CLK_NONE #define CONFIG_SYS_UEC8_ETH_TYPE GIGA_ETH #define CONFIG_SYS_UEC8_PHY_ADDR 6 -#define CONFIG_SYS_UEC8_INTERFACE_TYPE SGMII +#define CONFIG_SYS_UEC8_INTERFACE_TYPE PHY_INTERFACE_MODE_SGMII #define CONFIG_SYS_UEC8_INTERFACE_SPEED 1000 #endif /* CONFIG_UEC_ETH8 */ @@ -484,7 +478,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_PCI) -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ #undef CONFIG_EEPRO100 @@ -495,10 +488,6 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_PCI */ -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - /* * Environment */ @@ -519,7 +508,8 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FW_ADDR 0xfff00000 +#define CONFIG_SYS_QE_FMAN_FW_IN_NOR +#define CONFIG_SYS_QE_FMAN_FW_ADDR 0xfff00000 /* * BOOTP options @@ -585,11 +575,11 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 16 MB of memory, since this is + * have to be in the first 64 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (16 << 20) - /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -600,8 +590,8 @@ extern unsigned long get_clock_freq(void); * Environment Configuration */ #define CONFIG_HOSTNAME mpc8569mds -#define CONFIG_ROOTPATH /nfsroot -#define CONFIG_BOOTFILE your.uImage +#define CONFIG_ROOTPATH "/nfsroot" +#define CONFIG_BOOTFILE "your.uImage" #define CONFIG_SERVERIP 192.168.1.1 #define CONFIG_GATEWAYIP 192.168.1.1