X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8569MDS.h;h=acb8dec81927e1bfce85220a68055092fff3c9f8;hb=117c7ee283f1c3f49306fb11939b59fe11cbf5a8;hp=eb7db20b7f4fdfe80ff5e6f89f086cb1e99f6760;hpb=be62fbf376261ab3a4ed5db3bf54d5df9e216d9f;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index eb7db20..acb8dec 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2009-2011 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -16,9 +15,7 @@ #define CONFIG_PCIE1 1 /* PCIE controller */ #define CONFIG_FSL_PCI_INIT 1 /* use common fsl pci init code */ #define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ -#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_QE /* Enable QE */ #define CONFIG_ENV_OVERWRITE #ifndef __ASSEMBLY__ @@ -39,10 +36,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfff80000 -#endif - #ifndef CONFIG_SYS_MONITOR_BASE #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #endif @@ -52,12 +45,8 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_ENABLE_36BIT_PHYS 1 -#define CONFIG_BOARD_EARLY_INIT_R 1 #define CONFIG_HWCONFIG -#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x00400000 - /* * Config the L2 Cache as L2 SRAM */ @@ -74,7 +63,6 @@ extern unsigned long get_clock_freq(void); #endif /* DDR Setup */ -#undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ @@ -121,8 +109,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_ERR_DIS 0x00000000 #define CONFIG_SYS_DDR_SBE 0x00010000 -#undef CONFIG_CLOCKS_IN_MHZ - /* * Local Bus Definitions */ @@ -157,8 +143,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_SYS_RAMBOOT -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO /* Chip select 3 - NAND */ @@ -181,7 +165,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_NAND_BASE_PHYS CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE, } #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_CMD_NAND 1 #define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) #define CONFIG_SYS_NAND_BR_PRELIM (CONFIG_SYS_NAND_BASE_PHYS \ @@ -219,7 +202,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -412,8 +394,6 @@ extern unsigned long get_clock_freq(void); #endif /* CONFIG_QE */ #if defined(CONFIG_PCI) -#undef CONFIG_EEPRO100 -#undef CONFIG_TULIP #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ @@ -422,42 +402,21 @@ extern unsigned long get_clock_freq(void); /* * Environment */ -#if defined(CONFIG_SYS_RAMBOOT) -#else -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) -#define CONFIG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ -#define CONFIG_ENV_SIZE 0x2000 -#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ /* QE microcode/firmware address */ -#define CONFIG_SYS_QE_FMAN_FW_IN_NOR #define CONFIG_SYS_QE_FW_ADDR 0xfff00000 /* * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_ESDHC_PIN_MUX #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif @@ -465,17 +424,12 @@ extern unsigned long get_clock_freq(void); /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 2048 /* Console I/O Buffer Size */ #else #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ #endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) - /* Print Buffer Size */ #define CONFIG_SYS_MAXARGS 32 /* max number of command args */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ @@ -495,7 +449,7 @@ extern unsigned long get_clock_freq(void); /* * Environment Configuration */ -#define CONFIG_HOSTNAME mpc8569mds +#define CONFIG_HOSTNAME "mpc8569mds" #define CONFIG_ROOTPATH "/nfsroot" #define CONFIG_BOOTFILE "your.uImage" @@ -505,8 +459,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 200000 /*default location for tftp and bootm*/ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \