X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8568MDS.h;h=7bb20e58cae143923d83b9d27bb502f9fef62c75;hb=cfd60441d8360cb9ffa315ecf3a2aef9bc134905;hp=b9366cc99476dc70d2d1df7f025715c495cc0461;hpb=9caeaadf508cd0e11ac5dfc56ab0f72e3b89a105;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h
index b9366cc..7bb20e5 100644
--- a/include/configs/MPC8568MDS.h
+++ b/include/configs/MPC8568MDS.h
@@ -33,7 +33,11 @@
 #define CONFIG_MPC8568		1	/* MPC8568 specific */
 #define CONFIG_MPC8568MDS	1	/* MPC8568MDS board specific */
 
-#define CONFIG_PCI
+#define CONFIG_PCI		1	/* Enable PCI/PCIE */
+#define CONFIG_PCI1		1	/* PCI controller */
+#define CONFIG_PCIE1		1	/* PCIE controller */
+#define CONFIG_FSL_PCI_INIT	1	/* use common fsl pci init code */
+#define CONFIG_FSL_PCIE_RESET	1	/* need PCIe reset errata */
 #define CONFIG_TSEC_ENET 		/* tsec ethernet support */
 #define CONFIG_QE			/* Enable QE */
 #define CONFIG_ENV_OVERWRITE
@@ -45,6 +49,7 @@
 /*#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER*/	/* DDR controller or DMA? */
 #define CONFIG_MEM_INIT_VALUE		0xDeadBeef
 
+#define CONFIG_FSL_LAW		1	/* Use common FSL init code */
 
 /*
  * When initializing flash, if we cannot find the manufacturer ID,
@@ -85,8 +90,12 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_CCSRBAR_DEFAULT 	0xff700000	/* CCSRBAR Default */
 #define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR */
+#define CFG_CCSRBAR_PHYS	CFG_CCSRBAR	/* physical addr of CCSRBAR */
 #define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR */
 
+#define CFG_PCI1_ADDR           (CFG_CCSRBAR+0x8000)
+#define CFG_PCIE1_ADDR          (CFG_CCSRBAR+0xa000)
+
 /*
  * DDR Setup
  */
@@ -290,14 +299,9 @@ extern unsigned long get_clock_freq(void);
 #endif
 
 /* pass open firmware flat tree */
-#define CONFIG_OF_FLAT_TREE	1
-#define CONFIG_OF_BOARD_SETUP	1
-
-#define OF_CPU			"PowerPC,8568@0"
-#define OF_SOC			"soc8568@e0000000"
-#define OF_QE			"qe@e0080000"
-#define OF_TBCLK		(bd->bi_busfreq / 8)
-#define OF_STDOUT_PATH		"/soc8568@e0000000/serial@4500"
+#define CONFIG_OF_LIBFDT		1
+#define CONFIG_OF_BOARD_SETUP		1
+#define CONFIG_OF_STDOUT_VIA_ALIAS	1
 
 /*
  * I2C
@@ -325,12 +329,12 @@ extern unsigned long get_clock_freq(void);
 #define CFG_PCI1_IO_PHYS	0xe2000000
 #define CFG_PCI1_IO_SIZE	0x00800000	/* 8M */
 
-#define CFG_PEX_MEM_BASE	0xa0000000
-#define CFG_PEX_MEM_PHYS	CFG_PEX_MEM_BASE
-#define CFG_PEX_MEM_SIZE	0x10000000	/* 256M */
-#define CFG_PEX_IO_BASE		0x00000000
-#define CFG_PEX_IO_PHYS		0xe2800000
-#define CFG_PEX_IO_SIZE		0x00800000	/* 8M */
+#define CFG_PCIE1_MEM_BASE	0xa0000000
+#define CFG_PCIE1_MEM_PHYS	CFG_PCIE1_MEM_BASE
+#define CFG_PCIE1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_PCIE1_IO_BASE	0x00000000
+#define CFG_PCIE1_IO_PHYS	0xe2800000
+#define CFG_PCIE1_IO_SIZE	0x00800000	/* 8M */
 
 #define CFG_SRIO_MEM_BASE	0xc0000000
 
@@ -383,6 +387,11 @@ extern unsigned long get_clock_freq(void);
 #undef CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup */
 #define CFG_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */
 
+/* PCI view of System Memory */
+#define CFG_PCI_MEMORY_BUS      0x00000000
+#define CFG_PCI_MEMORY_PHYS     0x00000000
+#define CFG_PCI_MEMORY_SIZE     0x80000000
+
 #endif	/* CONFIG_PCI */
 
 #ifndef CONFIG_NET_MULTI
@@ -440,6 +449,7 @@ extern unsigned long get_clock_freq(void);
 #define CONFIG_CMD_PING
 #define CONFIG_CMD_I2C
 #define CONFIG_CMD_MII
+#define CONFIG_CMD_ELF
 
 #if defined(CONFIG_PCI)
     #define CONFIG_CMD_PCI
@@ -452,6 +462,7 @@ extern unsigned long get_clock_freq(void);
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory	*/
+#define CONFIG_CMDLINE_EDITING		/* Command-line editing */
 #define CFG_LOAD_ADDR	0x2000000	/* default load address */
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt */
 #if defined(CONFIG_CMD_KGDB)
@@ -471,13 +482,6 @@ extern unsigned long get_clock_freq(void);
  */
 #define CFG_BOOTMAPSZ	(8 << 20) 	/* Initial Memory map for Linux*/
 
-/* Cache Configuration */
-#define CFG_DCACHE_SIZE	32768
-#define CFG_CACHELINE_SIZE	32
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/*log base 2 of the above value*/
-#endif
-
 /*
  * Internal Definitions
  *