X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8548CDS.h;h=b09cbab292a6d44194bb96cbca2197720c3c9878;hb=87f78478a4a1bf574db0b0e575ca37cf91fb187c;hp=b81a4eddd784c53da3c2ca894390992ce38b77e7;hpb=9f03247edc7761b608db31104821b4518a70e691;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b81a4ed..b09cbab 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2004, 2007, 2010-2011 Freescale Semiconductor. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -13,26 +12,9 @@ #ifndef __CONFIG_H #define __CONFIG_H -#define CONFIG_DISPLAY_BOARDINFO - -#ifdef CONFIG_36BIT -#define CONFIG_PHYS_64BIT -#endif - -/* High Level Configuration Options */ -#define CONFIG_BOOKE 1 /* BOOKE */ -#define CONFIG_E500 1 /* BOOKE e500 family */ -#define CONFIG_MPC8548 1 /* MPC8548 specific */ -#define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ - -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xfff80000 -#endif - #define CONFIG_SYS_SRIO #define CONFIG_SRIO1 /* SRIO port 1 */ -#define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 @@ -41,10 +23,8 @@ #define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ -#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ -#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ #define CONFIG_FSL_VIA @@ -76,7 +56,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR /* DDR Setup */ -#define CONFIG_SYS_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD @@ -88,7 +67,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE -#define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_DIMM_SLOTS_PER_CTLR 1 #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) @@ -191,8 +169,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO #define CONFIG_HWCONFIG /* enable hwconfig */ @@ -319,7 +295,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserved for malloc */ /* Serial Port */ -#define CONFIG_CONS_INDEX 2 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -410,9 +385,6 @@ extern unsigned long get_clock_freq(void); #endif #if defined(CONFIG_PCI) - -#define CONFIG_PCI_PNP /* do pci plug-and-play */ - #undef CONFIG_EEPRO100 #undef CONFIG_TULIP @@ -422,7 +394,6 @@ extern unsigned long get_clock_freq(void); #if defined(CONFIG_TSEC_ENET) -#define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC0" #define CONFIG_TSEC2 1 @@ -433,8 +404,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_TSEC4_NAME "eTSEC3" #undef CONFIG_MPC85XX_FEC -#define CONFIG_PHY_MARVELL - #define TSEC1_PHY_ADDR 0 #define TSEC2_PHY_ADDR 1 #define TSEC3_PHY_ADDR 2 @@ -451,13 +420,11 @@ extern unsigned long get_clock_freq(void); /* Options are: eTSEC[0-3] */ #define CONFIG_ETHPRIME "eTSEC0" -#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ #endif /* CONFIG_TSEC_ENET */ /* * Environment */ -#define CONFIG_ENV_IS_IN_FLASH 1 #if CONFIG_SYS_MONITOR_BASE > 0xfff80000 #define CONFIG_ENV_ADDR 0xfff80000 #else @@ -473,37 +440,13 @@ extern unsigned long get_clock_freq(void); * BOOTP options */ #define CONFIG_BOOTP_BOOTFILESIZE -#define CONFIG_BOOTP_BOOTPATH -#define CONFIG_BOOTP_GATEWAY -#define CONFIG_BOOTP_HOSTNAME - -/* - * Command line configuration. - */ -#define CONFIG_CMD_IRQ -#define CONFIG_CMD_REGINFO - -#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI -#endif #undef CONFIG_WATCHDOG /* watchdog disabled */ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#if defined(CONFIG_CMD_KGDB) -#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ -#else -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#endif -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ /* * For booting Linux, the board info and command line data @@ -529,7 +472,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_IPADDR 192.168.1.253 -#define CONFIG_HOSTNAME unknown +#define CONFIG_HOSTNAME "unknown" #define CONFIG_ROOTPATH "/nfsroot" #define CONFIG_BOOTFILE "8548cds/uImage.uboot" #define CONFIG_UBOOTPATH 8548cds/u-boot.bin /* TFTP server */ @@ -540,10 +483,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_LOADADDR 1000000 /*default location for tftp and bootm*/ -#undef CONFIG_BOOTARGS /* the boot command will set bootargs*/ - -#define CONFIG_BAUDRATE 115200 - #define CONFIG_EXTRA_ENV_SETTINGS \ "hwconfig=fsl_ddr:ecc=off\0" \ "netdev=eth0\0" \