X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8548CDS.h;h=75ac269570787b3f69d4b7656b53e49c42fedff1;hb=19b4040df03813ffeb3af77d4f44b1b08013bf77;hp=d4a2b0184f64fbfdaae45918fb2ce9be439731ec;hpb=5d68d2f41df5099f890052756f14f5a810f34312;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index d4a2b01..75ac269 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -13,9 +13,6 @@
 #ifndef __CONFIG_H
 #define __CONFIG_H
 
-#define CONFIG_SYS_SRIO
-#define CONFIG_SRIO1			/* SRIO port 1 */
-
 #define CONFIG_INTERRUPTS		/* enable pci, srio, ddr interrupts */
 
 #ifndef __ASSEMBLY__
@@ -31,16 +28,16 @@
  * Only possible on E500 Version 2 or newer cores.
  */
 
-#define CONFIG_SYS_CCSRBAR		0xe0000000
-#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR
+#define CFG_SYS_CCSRBAR		0xe0000000
+#define CFG_SYS_CCSRBAR_PHYS_LOW	CFG_SYS_CCSRBAR
 
 /* DDR Setup */
 #define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
 
 #define CONFIG_MEM_INIT_VALUE	0xDeadBeef
 
-#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
-#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE
+#define CFG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
+#define CFG_SYS_SDRAM_BASE		CFG_SYS_DDR_SDRAM_BASE
 
 /* I2C addresses of SPD EEPROMs */
 #define SPD_EEPROM_ADDRESS	0x51	/* CTLR 0 DIMM 0 */
@@ -115,33 +112,30 @@
  * 1111 1111 1000 0000 0110 1110 0110 0101 = ff806e65	 ORx
  */
 
-#define CONFIG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
+#define CFG_SYS_FLASH_BASE		0xff000000	/* start of FLASH 16M */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_FLASH_BASE_PHYS	0xfff000000ull
+#define CFG_SYS_FLASH_BASE_PHYS	0xfff000000ull
 #else
-#define CONFIG_SYS_FLASH_BASE_PHYS	CONFIG_SYS_FLASH_BASE
+#define CFG_SYS_FLASH_BASE_PHYS	CFG_SYS_FLASH_BASE
 #endif
 
-#define CONFIG_SYS_FLASH_BANKS_LIST \
-	{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
-#define CONFIG_SYS_MAX_FLASH_SECT	128		/* sectors per device */
-
-#define CONFIG_HWCONFIG			/* enable hwconfig */
+#define CFG_SYS_FLASH_BANKS_LIST \
+	{CFG_SYS_FLASH_BASE_PHYS + 0x800000, CFG_SYS_FLASH_BASE_PHYS}
 
 /*
  * SDRAM on the Local Bus
  */
-#define CONFIG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
+#define CFG_SYS_LBC_SDRAM_BASE	0xf0000000	/* Localbus SDRAM */
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS	0xff0000000ull
 #else
-#define CONFIG_SYS_LBC_SDRAM_BASE_PHYS	CONFIG_SYS_LBC_SDRAM_BASE
+#define CFG_SYS_LBC_SDRAM_BASE_PHYS	CFG_SYS_LBC_SDRAM_BASE
 #endif
-#define CONFIG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
+#define CFG_SYS_LBC_SDRAM_SIZE	64		/* LBC SDRAM is 64MB */
 
 /*
  * Base Register 2 and Option Register 2 configure SDRAM.
- * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
+ * The SDRAM base address, CFG_SYS_LBC_SDRAM_BASE, is 0xf0000000.
  *
  * For BR2, need:
  *    Base address of 0xf0000000 = BR[0:16] = 1111 0000 0000 0000 0
@@ -153,12 +147,12 @@
  * 0	4    8	  12   16   20	 24   28
  * 1111 0000 0000 0000 0001 1000 0110 0001 = f0001861
  *
- * FIXME: CONFIG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
+ * FIXME: CFG_SYS_LBC_SDRAM_BASE should be masked and OR'ed into
  * FIXME: the top 17 bits of BR2.
  */
 
 /*
- * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
+ * The SDRAM size in MB, CFG_SYS_LBC_SDRAM_SIZE, is 64.
  *
  * For OR2, need:
  *    64MB mask for AM, OR2[0:7] = 1111 1100
@@ -171,10 +165,10 @@
  * 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
  */
 
-#define CONFIG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
-#define CONFIG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
-#define CONFIG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
-#define CONFIG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
+#define CFG_SYS_LBC_LCRR		0x00030004	/* LB clock ratio reg */
+#define CFG_SYS_LBC_LBCR		0x00000000	/* LB config reg */
+#define CFG_SYS_LBC_LSRT		0x20000000	/* LB sdram refresh timer */
+#define CFG_SYS_LBC_MRTPR		0x00000000	/* LB refresh timer prescal*/
 
 /*
  * Common settings for all Local Bus SDRAM commands.
@@ -182,7 +176,7 @@
  *		    or BSMA1617 (for CPU 1.0) (old)
  * is OR'ed in too.
  */
-#define CONFIG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
+#define CFG_SYS_LBC_LSDMR_COMMON	( LSDMR_RFCR16		\
 				| LSDMR_PRETOACT7	\
 				| LSDMR_ACTTORW7	\
 				| LSDMR_BL8		\
@@ -221,8 +215,6 @@
  * 1111 1111 1111 0000 0000 1111 1111 0111 = fff00ff7
  */
 
-#define CONFIG_FSL_CADMUS
-
 #define CADMUS_BASE_ADDR 0xf8000000
 #ifdef CONFIG_PHYS_64BIT
 #define CADMUS_BASE_ADDR_PHYS	0xff8000000ull
@@ -230,82 +222,69 @@
 #define CADMUS_BASE_ADDR_PHYS	CADMUS_BASE_ADDR
 #endif
 
-#define CONFIG_SYS_INIT_RAM_LOCK	1
-#define CONFIG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
-#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
+#define CFG_SYS_INIT_RAM_ADDR	0xe4010000	/* Initial RAM address */
+#define CFG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */
 
-#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-
-#define CONFIG_SYS_MONITOR_LEN		(512 * 1024)
+#define CFG_SYS_INIT_SP_OFFSET	(CFG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 
 /* Serial Port */
-#define CONFIG_SYS_NS16550_SERIAL
-#define CONFIG_SYS_NS16550_REG_SIZE	1
-#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)
+#define CFG_SYS_NS16550_CLK		get_bus_freq(0)
 
-#define CONFIG_SYS_BAUDRATE_TABLE \
+#define CFG_SYS_BAUDRATE_TABLE \
 	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
 
-#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
-#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)
+#define CFG_SYS_NS16550_COM1	(CFG_SYS_CCSRBAR+0x4500)
+#define CFG_SYS_NS16550_COM2	(CFG_SYS_CCSRBAR+0x4600)
 
 /*
  * I2C
  */
 #if !CONFIG_IS_ENABLED(DM_I2C)
-#define CONFIG_SYS_I2C_NOPROBES		{ {0, 0x69} }
+#define CFG_SYS_I2C_NOPROBES		{ {0, 0x69} }
 #endif
 
-/* EEPROM */
-#define CONFIG_SYS_I2C_EEPROM_CCID
-
 /*
  * General PCI
  * Memory space is mapped 1-1, but I/O space must start from 0.
  */
-#define CONFIG_SYS_PCI1_MEM_VIRT	0x80000000
+#define CFG_SYS_PCI1_MEM_VIRT	0x80000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_MEM_BUS		0xe0000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0xc00000000ull
+#define CFG_SYS_PCI1_MEM_PHYS	0xc00000000ull
 #else
-#define CONFIG_SYS_PCI1_MEM_BUS	0x80000000
-#define CONFIG_SYS_PCI1_MEM_PHYS	0x80000000
+#define CFG_SYS_PCI1_MEM_PHYS	0x80000000
 #endif
-#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
-#define CONFIG_SYS_PCI1_IO_VIRT	0xe2000000
-#define CONFIG_SYS_PCI1_IO_BUS	0x00000000
+#define CFG_SYS_PCI1_IO_VIRT	0xe2000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCI1_IO_PHYS 0xfe2000000ull
+#define CFG_SYS_PCI1_IO_PHYS 0xfe2000000ull
 #else
-#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
+#define CFG_SYS_PCI1_IO_PHYS	0xe2000000
 #endif
-#define CONFIG_SYS_PCI1_IO_SIZE	0x00100000	/* 1M */
 
 #ifdef CONFIG_PCIE1
-#define CONFIG_SYS_PCIE1_MEM_VIRT	0xa0000000
+#define CFG_SYS_PCIE1_MEM_VIRT	0xa0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
+#define CFG_SYS_PCIE1_MEM_PHYS	0xc20000000ull
 #else
-#define CONFIG_SYS_PCIE1_MEM_PHYS	0xa0000000
+#define CFG_SYS_PCIE1_MEM_PHYS	0xa0000000
 #endif
-#define CONFIG_SYS_PCIE1_IO_VIRT	0xe3000000
+#define CFG_SYS_PCIE1_IO_VIRT	0xe3000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
+#define CFG_SYS_PCIE1_IO_PHYS        0xfe3000000ull
 #else
-#define CONFIG_SYS_PCIE1_IO_PHYS	0xe3000000
+#define CFG_SYS_PCIE1_IO_PHYS	0xe3000000
 #endif
 #endif
 
 /*
  * RapidIO MMU
  */
-#define CONFIG_SYS_SRIO1_MEM_VIRT	0xc0000000
+#define CFG_SYS_SRIO1_MEM_VIRT	0xc0000000
 #ifdef CONFIG_PHYS_64BIT
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
+#define CFG_SYS_SRIO1_MEM_PHYS	0xc40000000ull
 #else
-#define CONFIG_SYS_SRIO1_MEM_PHYS	0xc0000000
+#define CFG_SYS_SRIO1_MEM_PHYS	0xc0000000
 #endif
-#define CONFIG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
+#define CFG_SYS_SRIO1_MEM_SIZE	0x20000000	/* 512M */
 
 #if defined(CONFIG_TSEC_ENET)
 
@@ -335,13 +314,6 @@
 #endif	/* CONFIG_TSEC_ENET */
 
 /*
- * Environment
- */
-
-#define CONFIG_LOADS_ECHO	1	/* echo on for serial download */
-#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change */
-
-/*
  * Miscellaneous configurable options
  */
 
@@ -350,7 +322,7 @@
  * have to be in the first 64 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization.
  */
-#define CONFIG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
+#define CFG_SYS_BOOTMAPSZ	(64 << 20)	/* Initial Memory map for Linux*/
 
 /*
  * Environment Configuration
@@ -371,15 +343,15 @@
 	"netdev=eth0\0"				\
 	"uboot=" __stringify(CONFIG_UBOOTPATH) "\0"	\
 	"tftpflash=tftpboot $loadaddr $uboot; "	\
-		"protect off " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		"protect off " __stringify(CONFIG_TEXT_BASE)	\
 			" +$filesize; "	\
-		"erase " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		"erase " __stringify(CONFIG_TEXT_BASE)		\
 			" +$filesize; "	\
-		"cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		"cp.b $loadaddr " __stringify(CONFIG_TEXT_BASE)	\
 			" $filesize; "	\
-		"protect on " __stringify(CONFIG_SYS_TEXT_BASE)		\
+		"protect on " __stringify(CONFIG_TEXT_BASE)		\
 			" +$filesize; "	\
-		"cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE)	\
+		"cmp.b $loadaddr " __stringify(CONFIG_TEXT_BASE)	\
 			" $filesize\0"	\
 	"consoledev=ttyS1\0"			\
 	"ramdiskaddr=2000000\0"			\