X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8548CDS.h;h=5d21d116f99f0128be09e7b87e53667d1a267835;hb=37a3bda0c9c8a2ffbf7e2a9e121177a3385a0626;hp=083afba9a3073f27bc2f3b721425832970701cda;hpb=f8030519bbe20b836f3939742b959cbadfaad51b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 083afba..5d21d11 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -36,6 +36,10 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_MPC8548CDS 1 /* MPC8548CDS board specific */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xfff80000 +#endif + #define CONFIG_PCI /* enable any pci type devices */ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ @@ -52,13 +56,6 @@ #define CONFIG_FSL_VIA -/* - * When initializing flash, if we cannot find the manufacturer ID, - * assume this is the AMD flash associated with the CDS board. - * This allows booting from a promjet. - */ -#define CONFIG_ASSUME_AMD_FLASH - #ifndef __ASSEMBLY__ extern unsigned long get_clock_freq(void); #endif @@ -69,8 +66,6 @@ extern unsigned long get_clock_freq(void); */ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ -#define CONFIG_CLEAR_LAW0 /* Clear LAW0 in cpu_init_r */ /* * Only possible on E500 Version 2 or newer cores. @@ -89,10 +84,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ -#define CONFIG_SYS_PCI1_ADDR (CONFIG_SYS_CCSRBAR+0x8000) -#define CONFIG_SYS_PCI2_ADDR (CONFIG_SYS_CCSRBAR+0x9000) -#define CONFIG_SYS_PCIE1_ADDR (CONFIG_SYS_CCSRBAR+0xa000) - /* DDR Setup */ #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE @@ -100,7 +91,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_DDR_SPD #define CONFIG_DDR_DLL /* possible DLL fix needed */ -#undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ @@ -170,7 +161,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_FLASH_CFI @@ -230,41 +221,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_LBC_MRTPR 0x00000000 /* LB refresh timer prescal*/ /* - * LSDMR masks - */ -#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -/* * Common settings for all Local Bus SDRAM commands. * At run time, either BSMA1516 (for CPU 1.1) * or BSMA1617 (for CPU 1.0) (old) * is OR'ed in too. */ -#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFCR16 \ - | CONFIG_SYS_LBC_LSDMR_PRETOACT7 \ - | CONFIG_SYS_LBC_LSDMR_ACTTORW7 \ - | CONFIG_SYS_LBC_LSDMR_BL8 \ - | CONFIG_SYS_LBC_LSDMR_WRC4 \ - | CONFIG_SYS_LBC_LSDMR_CL3 \ - | CONFIG_SYS_LBC_LSDMR_RFEN \ +#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFCR16 \ + | LSDMR_PRETOACT7 \ + | LSDMR_ACTTORW7 \ + | LSDMR_BL8 \ + | LSDMR_WRC4 \ + | LSDMR_CL3 \ + | LSDMR_RFEN \ ) /* @@ -303,7 +271,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_BR3_PRELIM 0xf8000801 #define CONFIG_SYS_OR3_PRELIM 0xfff00ff7 -#define CONFIG_L1_INIT_RAM #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */ @@ -319,7 +286,6 @@ extern unsigned long get_clock_freq(void); /* Serial Port */ #define CONFIG_CONS_INDEX 2 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -342,9 +308,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_OF_BOARD_SETUP 1 #define CONFIG_OF_STDOUT_VIA_ALIAS 1 -#define CONFIG_SYS_64BIT_VSPRINTF 1 -#define CONFIG_SYS_64BIT_STRTOUL 1 - /* * I2C */ @@ -367,29 +330,36 @@ extern unsigned long get_clock_freq(void); * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */ -#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ #ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE +#define CONFIG_SYS_PCI2_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCI2_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 +#define CONFIG_SYS_PCI2_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCI2_IO_BUS 0x00000000 #define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 #define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ #endif #ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif @@ -398,7 +368,8 @@ extern unsigned long get_clock_freq(void); /* * RapidIO MMU */ -#define CONFIG_SYS_RIO_MEM_BASE 0xC0000000 +#define CONFIG_SYS_RIO_MEM_VIRT 0xC0000000 +#define CONFIG_SYS_RIO_MEM_BUS 0xC0000000 #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif @@ -490,6 +461,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_ELF #define CONFIG_CMD_IRQ #define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -502,7 +474,8 @@ extern unsigned long get_clock_freq(void); * Miscellaneous configurable options */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -517,18 +490,10 @@ extern unsigned long get_clock_freq(void); /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 16 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ - -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SYS_BOOTMAPSZ (16 << 20) /* Initial Memory map for Linux*/ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ @@ -573,11 +538,11 @@ extern unsigned long get_clock_freq(void); "netdev=eth0\0" \ "uboot=" MK_STR(CONFIG_UBOOTPATH) "\0" \ "tftpflash=tftpboot $loadaddr $uboot; " \ - "protect off " MK_STR(TEXT_BASE) " +$filesize; " \ - "erase " MK_STR(TEXT_BASE) " +$filesize; " \ - "cp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize; " \ - "protect on " MK_STR(TEXT_BASE) " +$filesize; " \ - "cmp.b $loadaddr " MK_STR(TEXT_BASE) " $filesize\0" \ + "protect off " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "erase " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize; " \ + "protect on " MK_STR(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cmp.b $loadaddr " MK_STR(CONFIG_SYS_TEXT_BASE) " $filesize\0" \ "consoledev=ttyS1\0" \ "ramdiskaddr=2000000\0" \ "ramdiskfile=ramdisk.uboot\0" \