X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC837XERDB.h;h=e299437a82386bec25bfe5ea04d351ff71dceae1;hb=72d81360aabd0485d3832d292bbea29c7c4554ef;hp=772ce6d4a8a0b8cea04f220a469fad4482fb0b79;hpb=e12546de54fc9be818e8d39967b07fa351d9e5ba;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 772ce6d..e299437 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -1,94 +1,30 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright (C) 2007 Freescale Semiconductor, Inc. * Kevin Lam * Joe D'Abbraccio - * - * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H #define __CONFIG_H +#include + /* * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 family */ -#define CONFIG_MPC837x 1 /* MPC837x CPU specific */ -#define CONFIG_MPC837XERDB 1 -#define CONFIG_MISC_INIT_R #define CONFIG_HWCONFIG /* * On-board devices */ -#define CONFIG_TSEC_ENET /* TSEC Ethernet support */ #define CONFIG_VSC7385_ENET -/* - * System Clock Setup - */ -#ifdef CONFIG_PCISLAVE -#define CONFIG_83XX_PCICLK 66666667 /* in HZ */ -#else -#define CONFIG_83XX_CLKIN 66666667 /* in Hz */ -#define CONFIG_PCIE -#endif - -#ifndef CONFIG_SYS_CLK_FREQ -#define CONFIG_SYS_CLK_FREQ CONFIG_83XX_CLKIN -#endif - -/* - * Hardware Reset Configuration Word - */ -#define CONFIG_SYS_HRCW_LOW (\ - HRCWL_LCL_BUS_TO_SCB_CLK_1X1 |\ - HRCWL_DDR_TO_SCB_CLK_1X1 |\ - HRCWL_SVCOD_DIV_2 |\ - HRCWL_CSB_TO_CLKIN_5X1 |\ - HRCWL_CORE_TO_CSB_2X1) - -#ifdef CONFIG_PCISLAVE -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_AGENT |\ - HRCWH_PCI1_ARBITER_DISABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0XFFF00100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#else -#define CONFIG_SYS_HRCW_HIGH (\ - HRCWH_PCI_HOST |\ - HRCWH_PCI1_ARBITER_ENABLE |\ - HRCWH_CORE_ENABLE |\ - HRCWH_FROM_0X00000100 |\ - HRCWH_BOOTSEQ_DISABLE |\ - HRCWH_SW_WATCHDOG_DISABLE |\ - HRCWH_ROM_LOC_LOCAL_16BIT |\ - HRCWH_RL_EXT_LEGACY |\ - HRCWH_TSEC1M_IN_RGMII |\ - HRCWH_TSEC2M_IN_RGMII |\ - HRCWH_BIG_ENDIAN |\ - HRCWH_LDP_CLEAR) -#endif - /* System performance - define the value i.e. CONFIG_SYS_XXX */ -/* Arbiter Configuration Register */ -#define CONFIG_SYS_ACR_PIPE_DEP 3 /* Arbiter pipeline depth (0-3) */ -#define CONFIG_SYS_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ - -/* System Priority Control Regsiter */ -#define CONFIG_SYS_SPCR_TSECEP 3 /* eTSEC1&2 emergency priority (0-3) */ - /* System Clock Configuration Register */ #define CONFIG_SYS_SCCR_TSEC1CM 1 /* eTSEC1 clock mode (0-3) */ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* eTSEC2 clock mode (0-3) */ @@ -106,11 +42,6 @@ #define CONFIG_SYS_OBIR 0x30100000 /* - * IMMR new address - */ -#define CONFIG_SYS_IMMR 0xE0000000 - -/* * Device configurations */ @@ -129,17 +60,12 @@ /* * DDR Setup */ -#define CONFIG_SYS_DDR_BASE 0x00000000 /* DDR is system memory */ -#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_BASE -#define CONFIG_SYS_DDR_SDRAM_BASE CONFIG_SYS_DDR_BASE +#define CONFIG_SYS_SDRAM_BASE 0x00000000 /* DDR is system memory */ #define CONFIG_SYS_DDR_SDRAM_CLK_CNTL 0x03000000 #define CONFIG_SYS_83XX_DDR_USES_CS0 #define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN | DDRCDR_ODT | DDRCDR_Q_DRN) -#undef CONFIG_DDR_ECC /* support DDR ECC function */ -#undef CONFIG_DDR_ECC_CMD /* Use DDR ECC user commands */ - #undef CONFIG_NEVER_ASSERT_ODT_TO_CPU /* Never assert ODT to internal IOs */ /* @@ -184,17 +110,9 @@ | (0 << SDRAM_INTERVAL_BSTOPRE_SHIFT)) /* 0x06090100 */ -#if defined(CONFIG_DDR_2T_TIMING) -#define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ - | SDRAM_CFG_SDRAM_TYPE_DDR2 \ - | SDRAM_CFG_32_BE \ - | SDRAM_CFG_2T_EN) - /* 0x43088000 */ -#else #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2) /* 0x43000000 */ -#endif #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 /* 1 posted refresh */ #define CONFIG_SYS_DDR_MODE ((0x0406 << SDRAM_MODE_ESD_SHIFT) \ | (0x0442 << SDRAM_MODE_SD_SHIFT)) @@ -205,8 +123,6 @@ * Memory test */ #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ -#define CONFIG_SYS_MEMTEST_START 0x00040000 /* memtest region */ -#define CONFIG_SYS_MEMTEST_END 0x0ef70010 /* * The reserved memory @@ -232,39 +148,13 @@ (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) /* - * Local Bus Configuration & Clock Setup - */ -#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP -#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_8 -#define CONFIG_SYS_LBC_LBCR 0x00000000 -#define CONFIG_FSL_ELBC 1 - -/* * FLASH on the Local Bus */ -#define CONFIG_SYS_FLASH_CFI /* use the Common Flash Interface */ -#define CONFIG_FLASH_CFI_DRIVER /* use the CFI driver */ #define CONFIG_SYS_FLASH_BASE 0xFE000000 /* FLASH base address */ #define CONFIG_SYS_FLASH_SIZE 8 /* max FLASH size is 32M */ -#define CONFIG_SYS_FLASH_PROTECTION 1 /* Use h/w Flash protection. */ #define CONFIG_SYS_FLASH_EMPTY_INFO /* display empty sectors */ -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* buffer up multiple bytes */ - - /* Window base at flash base */ -#define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000016 /* 8 MB window size */ - -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | BR_PS_16 /* 16 bit port */ \ - | BR_MS_GPCM /* MSEL = GPCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_9 \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xFF800191 */ + #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max sectors per device */ @@ -277,52 +167,15 @@ * NAND Flash on the Local Bus */ #define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ - | BR_DECC_CHK_GEN /* Use HW ECC */ \ - | BR_PS_8 /* 8 bit port */ \ - | BR_MS_FCM /* MSEL = FCM */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR1_PRELIM (OR_AM_32KB \ - | OR_FCM_CSCT \ - | OR_FCM_CST \ - | OR_FCM_CHT \ - | OR_FCM_SCY_1 \ - | OR_FCM_TRLX \ - | OR_FCM_EHTR) -#define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_32KB) + /* Vitesse 7385 */ #define CONFIG_SYS_VSC7385_BASE 0xF0000000 -#ifdef CONFIG_VSC7385_ENET - -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VSC7385_BASE \ - | BR_PS_8 \ - | BR_MS_GPCM \ - | BR_V) - /* 0xF0000801 */ -#define CONFIG_SYS_OR2_PRELIM (OR_AM_128KB \ - | OR_GPCM_CSNT \ - | OR_GPCM_XACS \ - | OR_GPCM_SCY_15 \ - | OR_GPCM_SETA \ - | OR_GPCM_TRLX_SET \ - | OR_GPCM_EHTR_SET \ - | OR_GPCM_EAD) - /* 0xfffe09ff */ - - /* Access Base */ -#define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VSC7385_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_128KB) - -#endif - /* * Serial Port */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -339,11 +192,6 @@ #define CONFIG_FSL_SERDES2 0xe3100 /* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_FSL -#define CONFIG_SYS_FSL_I2C_SPEED 400000 -#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F -#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 #define CONFIG_SYS_I2C_NOPROBES { {0, 0x51} } /* @@ -394,7 +242,6 @@ #define CONFIG_PCI_INDIRECT_BRIDGE #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1957 /* Freescale */ #endif /* CONFIG_PCI */ /* @@ -449,15 +296,6 @@ /* * Environment */ -#ifndef CONFIG_SYS_RAMBOOT - #define CONFIG_ENV_ADDR \ - (CONFIG_SYS_MONITOR_BASE+CONFIG_SYS_MONITOR_LEN) - #define CONFIG_ENV_SECT_SIZE 0x10000 /* 64K (one sector) for env */ - #define CONFIG_ENV_SIZE 0x4000 -#else - #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-0x1000) - #define CONFIG_ENV_SIZE 0x2000 -#endif #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ @@ -467,14 +305,9 @@ */ #define CONFIG_BOOTP_BOOTFILESIZE -/* - * Command line configuration. - */ - #undef CONFIG_WATCHDOG /* watchdog disabled */ #ifdef CONFIG_MMC -#define CONFIG_FSL_ESDHC #define CONFIG_FSL_ESDHC_PIN_MUX #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR #endif @@ -492,124 +325,6 @@ #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ -/* - * Core HID Setup - */ -#define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK \ - | HID0_ENABLE_INSTRUCTION_CACHE) -#define CONFIG_SYS_HID2 HID2_HBE - -/* - * MMU Setup - */ - -#define CONFIG_HIGH_BATS 1 /* High BATs supported */ - -/* DDR: cache cacheable */ -#define CONFIG_SYS_SDRAM_LOWER CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_SDRAM_UPPER (CONFIG_SYS_SDRAM_BASE + 0x10000000) - -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_LOWER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_LOWER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT0L CONFIG_SYS_IBAT0L -#define CONFIG_SYS_DBAT0U CONFIG_SYS_IBAT0U - -#define CONFIG_SYS_IBAT1L (CONFIG_SYS_SDRAM_UPPER \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT1U (CONFIG_SYS_SDRAM_UPPER \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT1L CONFIG_SYS_IBAT1L -#define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U - -/* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR \ - | BATU_BL_8M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT2L CONFIG_SYS_IBAT2L -#define CONFIG_SYS_DBAT2U CONFIG_SYS_IBAT2U - -/* L2 Switch: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT3L (CONFIG_SYS_VSC7385_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT3U (CONFIG_SYS_VSC7385_BASE \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT3L CONFIG_SYS_IBAT3L -#define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U - -/* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE \ - | BATU_BL_32M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U - -/* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) -#define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR \ - | BATU_BL_128K \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L -#define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U - -#ifdef CONFIG_PCI -/* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS \ - | BATL_PP_RW \ - | BATL_MEMCOHERENCE) -#define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -/* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATL_PP_RW \ - | BATL_CACHEINHIBIT \ - | BATL_GUARDEDSTORAGE) -#define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS \ - | BATU_BL_256M \ - | BATU_VS \ - | BATU_VP) -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#else -#define CONFIG_SYS_IBAT6L (0) -#define CONFIG_SYS_IBAT6U (0) -#define CONFIG_SYS_IBAT7L (0) -#define CONFIG_SYS_IBAT7U (0) -#define CONFIG_SYS_DBAT6L CONFIG_SYS_IBAT6L -#define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U -#define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L -#define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -#endif - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #endif @@ -617,7 +332,6 @@ /* * Environment Configuration */ -#define CONFIG_ENV_OVERWRITE #define CONFIG_HAS_FSL_DR_USB #define CONFIG_USB_EHCI_FSL @@ -625,7 +339,7 @@ #define CONFIG_NETDEV "eth1" -#define CONFIG_HOSTNAME mpc837x_rdb +#define CONFIG_HOSTNAME "mpc837x_rdb" #define CONFIG_ROOTPATH "/nfsroot" #define CONFIG_RAMDISKFILE "rootfs.ext2.gz.uboot" #define CONFIG_BOOTFILE "uImage" @@ -633,9 +347,6 @@ #define CONFIG_UBOOTPATH "u-boot.bin" #define CONFIG_FDTFILE "mpc8379_rdb.dtb" - /* default location for tftp and bootm */ -#define CONFIG_LOADADDR 800000 - #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=" CONFIG_NETDEV "\0" \ "uboot=" CONFIG_UBOOTPATH "\0" \ @@ -662,7 +373,7 @@ "$netdev:off " \ "root=$rootdev rw console=$console,$baudrate $othbootargs\0" -#define CONFIG_NFSBOOTCOMMAND \ +#define NFSBOOTCOMMAND \ "setenv rootdev /dev/nfs;" \ "run setbootargs;" \ "run setipargs;" \ @@ -670,7 +381,7 @@ "tftp $fdtaddr $fdtfile;" \ "bootm $loadaddr - $fdtaddr" -#define CONFIG_RAMBOOTCOMMAND \ +#define RAMBOOTCOMMAND \ "setenv rootdev /dev/ram;" \ "run setbootargs;" \ "tftp $ramdiskaddr $ramdiskfile;" \