X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8360ERDK.h;h=1b8bad179b5221ce18daec4f127eb5db18e09e10;hb=d5325eff10922acb11c39efece6d5f24de5b1998;hp=f56561394312c28f733e89ffd49d74e2821df236;hpb=9a9865508f76d512707f4ad8c21f4b9bbeadc5e3;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index f565613..1b8bad1 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -8,10 +8,7 @@ * Copyright (C) 2007 MontaVista Software, Inc. * Anton Vorontsov * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -22,7 +19,6 @@ */ #define CONFIG_E300 1 /* E300 family */ #define CONFIG_QE 1 /* Has QE */ -#define CONFIG_MPC83xx 1 /* MPC83xx family */ #define CONFIG_MPC8360 1 /* MPC8360 CPU specific */ #define CONFIG_MPC8360ERDK 1 /* MPC8360ERDK board specific */ @@ -96,7 +92,10 @@ /* * DDRCDR - DDR Control Driver Register */ -#define CONFIG_SYS_DDRCDR_VALUE 0x80080001 +#define CONFIG_SYS_DDRCDR_VALUE (DDRCDR_DHC_EN \ + | DDRCDR_ODT \ + | DDRCDR_Q_DRN) + /* 0x80080001 */ #undef CONFIG_SPD_EEPROM /* Do not use SPD EEPROM for DDR setup */ @@ -105,11 +104,11 @@ */ #define CONFIG_DDR_II #define CONFIG_SYS_DDR_SIZE 256 /* MB */ -#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f +#define CONFIG_SYS_DDR_CS0_BNDS 0x0000000f #define CONFIG_SYS_DDR_CS0_CONFIG (CSCONFIG_EN \ | CSCONFIG_ROW_BIT_13 \ | CSCONFIG_COL_BIT_10 \ - | CSCONFIG_ODT_WR_ACS) + | CSCONFIG_ODT_WR_ONLY_CURRENT) #define CONFIG_SYS_DDR_SDRAM_CFG (SDRAM_CFG_SDRAM_TYPE_DDR2 \ | SDRAM_CFG_ECC_EN) #define CONFIG_SYS_DDR_SDRAM_CFG2 0x00001000 @@ -167,7 +166,7 @@ #endif #define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ -#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ /* * Initial RAM Base Address Setup @@ -195,19 +194,20 @@ /* Window base at flash base */ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_LBLAWAR0_PRELIM 0x80000018 /* 32MB window size */ +#define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_32MB) #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \ - | (2 << BR_PS_SHIFT) /* 16 bit port */ \ - | BR_V) /* valid */ -#define CONFIG_SYS_OR0_PRELIM ((~(CONFIG_SYS_FLASH_SIZE - 1) << 20) \ + | BR_PS_16 /* 16 bit port */ \ + | BR_MS_GPCM /* MSEL = GPCM */ \ + | BR_V) /* valid */ +#define CONFIG_SYS_OR0_PRELIM (MEG_TO_AM(CONFIG_SYS_FLASH_SIZE) \ | OR_UPM_XAM \ | OR_GPCM_CSNT \ | OR_GPCM_ACS_DIV2 \ | OR_GPCM_XACS \ | OR_GPCM_SCY_15 \ - | OR_GPCM_TRLX \ - | OR_GPCM_EHTR \ + | OR_GPCM_TRLX_SET \ + | OR_GPCM_EHTR_SET \ | OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ @@ -225,11 +225,20 @@ #define CONFIG_MTD_NAND_VERIFY_WRITE #define CONFIG_SYS_LBLAWBAR1_PRELIM CONFIG_SYS_NAND_BASE -#define CONFIG_SYS_LBLAWAR1_PRELIM 0x8000001b /* Access window size 4K */ +/* + * [RFC] Comment said 4KB window; code said 256MB window; OR1 says 64MB + * ... What's correct? + */ +#define CONFIG_SYS_LBLAWAR1_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) /* Port size 8 bit, UPMA */ -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | 0x00000881) -#define CONFIG_SYS_OR1_PRELIM 0xfc000001 +#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE \ + | BR_PS_8 \ + | BR_MS_UPMA \ + | BR_V) + /* 0x60000881 */ +#define CONFIG_SYS_OR1_PRELIM (OR_AM_64MB | OR_UPM_EAD) + /* 0xFC000001 */ /* * Fujitsu MB86277 (MINT) graphics controller @@ -237,12 +246,16 @@ #define CONFIG_SYS_VIDEO_BASE 0x70000000 #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_VIDEO_BASE -#define CONFIG_SYS_LBLAWAR2_PRELIM 0x80000019 /* Access window size 64MB */ +#define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) /* Port size 32 bit, UPMB */ - /* PS=11, UPMB */ -#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE | 0x000018a1) -#define CONFIG_SYS_OR2_PRELIM 0xfc000001 /* (64MB, EAD=1) */ +#define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_VIDEO_BASE \ + | BR_PS_32 \ + | BR_MS_UPMB \ + | BR_V) + /* 0x000018a1 */ +#define CONFIG_SYS_OR2_PRELIM (OR_AM_64MB | OR_UPM_EAD) + /* 0xFC000001 */ /* * Serial Port @@ -263,9 +276,6 @@ #define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif /* Pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -273,15 +283,15 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS /* I2C */ -#define CONFIG_HARD_I2C /* I2C with hardware support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* Don't probe these addrs */ -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x52} } /* * General PCI @@ -300,6 +310,7 @@ #define CONFIG_SYS_PCI1_IO_SIZE 0x100000 /* 1M */ #ifdef CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP /* do pci plug-and-play */ @@ -393,7 +404,6 @@ */ #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -406,7 +416,6 @@ #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ /* Boot Argument Buffer Size */ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1ms ticks */ /* * For booting Linux, the board info and command line data @@ -431,7 +440,7 @@ /* DDR: cache cacheable */ #define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM_BASE \ | BATU_BL_256M \ @@ -442,7 +451,7 @@ /* IMMRBAR & PCI IO: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT1L (CONFIG_SYS_IMMR \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT1U (CONFIG_SYS_IMMR \ @@ -454,7 +463,7 @@ /* NAND: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT2L (CONFIG_SYS_NAND_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_NAND_BASE \ @@ -466,21 +475,21 @@ /* FLASH: icache cacheable, but dcache-inhibit and guarded */ #define CONFIG_SYS_IBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT3U (CONFIG_SYS_FLASH_BASE \ | BATU_BL_32M \ | BATU_VS \ | BATU_VP) #define CONFIG_SYS_DBAT3L (CONFIG_SYS_FLASH_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* Stack in dcache: cacheable, no memory coherence */ #define CONFIG_SYS_IBAT4L (CONFIG_SYS_INIT_RAM_ADDR \ - | BATL_PP_10) + | BATL_PP_RW) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_INIT_RAM_ADDR \ | BATU_BL_128K \ | BATU_VS \ @@ -489,7 +498,7 @@ #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U #define CONFIG_SYS_IBAT5L (CONFIG_SYS_VIDEO_BASE \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_VIDEO_BASE \ @@ -502,7 +511,7 @@ #ifdef CONFIG_PCI /* PCI MEM space: cacheable */ #define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI1_MEM_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI1_MEM_PHYS \ | BATU_BL_256M \ @@ -512,7 +521,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ #define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI1_MMIO_PHYS \ - | BATL_PP_10 \ + | BATL_PP_RW \ | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI1_MMIO_PHYS \ @@ -534,7 +543,6 @@ #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ -#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /*