X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8349EMDS.h;h=865d3176a5c6bfebf435c1bfc0c5fb2794d52f4f;hb=62a22dca32b988cce5d1908e8ac9fadb139bb3e8;hp=b3c0e2dd5c1db82754951eab6d600b00634b0f92;hpb=ea393eb1d6a786fc2e895f90abb5f7e7541aef45;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index b3c0e2d..865d317 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2006 + * (C) Copyright 2006-2010 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -33,16 +33,15 @@ * High Level Configuration Options */ #define CONFIG_E300 1 /* E300 Family */ -#define CONFIG_MPC83XX 1 /* MPC83XX family */ -#define CONFIG_MPC834X 1 /* MPC834X family */ +#define CONFIG_MPC83xx 1 /* MPC83xx family */ +#define CONFIG_MPC834x 1 /* MPC834x family */ #define CONFIG_MPC8349 1 /* MPC8349 specific */ #define CONFIG_MPC8349EMDS 1 /* MPC8349EMDS board specific */ -#undef CONFIG_PCI -#undef CONFIG_MPC83XX_PCI2 /* support for 2nd PCI controller */ +#define CONFIG_SYS_TEXT_BASE 0xFE000000 -#define PCI_66M -#ifdef PCI_66M +#define CONFIG_PCI_66M +#ifdef CONFIG_PCI_66M #define CONFIG_83XX_CLKIN 66000000 /* in Hz */ #else #define CONFIG_83XX_CLKIN 33000000 /* in Hz */ @@ -54,7 +53,7 @@ #endif /* CONFIG_PCISLAVE */ #ifndef CONFIG_SYS_CLK_FREQ -#ifdef PCI_66M +#ifdef CONFIG_PCI_66M #define CONFIG_SYS_CLK_FREQ 66000000 #define HRCWL_CSB_TO_CLKIN HRCWL_CSB_TO_CLKIN_4X1 #else @@ -79,6 +78,22 @@ #define CONFIG_SPD_EEPROM /* use SPD EEPROM for DDR setup*/ /* + * define CONFIG_FSL_DDR2 to use unified DDR driver + * undefine it to use old spd_sdram.c + */ +#define CONFIG_FSL_DDR2 +#ifdef CONFIG_FSL_DDR2 +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS1 0x52 +#define SPD_EEPROM_ADDRESS2 0x51 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_DIMM_SLOTS_PER_CTLR 2 +#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#endif + +/* * 32-bit data path mode. * * Please note that using this mode for devices with the real density of 64-bit @@ -175,8 +190,7 @@ #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ -#define CONFIG_SYS_MID_FLASH_JUMP 0x7F000000 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) #define CONFIG_SYS_RAMBOOT @@ -195,13 +209,12 @@ #define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xFD000000 /* Initial RAM address */ -#define CONFIG_SYS_INIT_RAM_END 0x1000 /* End of used area in RAM*/ +#define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM*/ -#define CONFIG_SYS_GBL_DATA_SIZE 0x100 /* num bytes initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ +#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Mon */ #define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ /* @@ -210,7 +223,8 @@ * External Local Bus rate is * CLKIN * HRCWL_CSB_TO_CLKIN / HRCWL_LCL_BUS_TO_SCB_CLK / LCRR_CLKDIV */ -#define CONFIG_SYS_LCRR (LCRR_DBYP | LCRR_CLKDIV_4) +#define CONFIG_SYS_LCRR_DBYP LCRR_DBYP +#define CONFIG_SYS_LCRR_CLKDIV LCRR_CLKDIV_4 #define CONFIG_SYS_LBC_LBCR 0x00000000 /* @@ -262,67 +276,30 @@ #define CONFIG_SYS_LBC_LSRT 0x32000000 /* LB sdram refresh timer, about 6us */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer prescal, 266MHz/32 */ -/* - * LSDMR masks - */ -#define CONFIG_SYS_LBC_LSDMR_RFEN (1 << (31 - 1)) -#define CONFIG_SYS_LBC_LSDMR_BSMA1516 (3 << (31 - 10)) -#define CONFIG_SYS_LBC_LSDMR_BSMA1617 (4 << (31 - 10)) -#define CONFIG_SYS_LBC_LSDMR_RFCR5 (3 << (31 - 16)) -#define CONFIG_SYS_LBC_LSDMR_RFCR8 (5 << (31 - 16)) -#define CONFIG_SYS_LBC_LSDMR_RFCR16 (7 << (31 - 16)) -#define CONFIG_SYS_LBC_LSDMR_PRETOACT3 (3 << (31 - 19)) -#define CONFIG_SYS_LBC_LSDMR_PRETOACT6 (5 << (31 - 19)) -#define CONFIG_SYS_LBC_LSDMR_PRETOACT7 (7 << (31 - 19)) -#define CONFIG_SYS_LBC_LSDMR_ACTTORW3 (3 << (31 - 22)) -#define CONFIG_SYS_LBC_LSDMR_ACTTORW7 (7 << (31 - 22)) -#define CONFIG_SYS_LBC_LSDMR_ACTTORW6 (6 << (31 - 22)) -#define CONFIG_SYS_LBC_LSDMR_BL8 (1 << (31 - 23)) -#define CONFIG_SYS_LBC_LSDMR_WRC2 (2 << (31 - 27)) -#define CONFIG_SYS_LBC_LSDMR_WRC3 (3 << (31 - 27)) -#define CONFIG_SYS_LBC_LSDMR_WRC4 (0 << (31 - 27)) -#define CONFIG_SYS_LBC_LSDMR_BUFCMD (1 << (31 - 29)) -#define CONFIG_SYS_LBC_LSDMR_CL3 (3 << (31 - 31)) - -#define CONFIG_SYS_LBC_LSDMR_OP_NORMAL (0 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_ARFRSH (1 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_SRFRSH (2 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_MRW (3 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_PRECH (4 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_PCHALL (5 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_ACTBNK (6 << (31 - 4)) -#define CONFIG_SYS_LBC_LSDMR_OP_RWINV (7 << (31 - 4)) - -#define CONFIG_SYS_LBC_LSDMR_COMMON ( CONFIG_SYS_LBC_LSDMR_RFEN \ - | CONFIG_SYS_LBC_LSDMR_BSMA1516 \ - | CONFIG_SYS_LBC_LSDMR_RFCR8 \ - | CONFIG_SYS_LBC_LSDMR_PRETOACT6 \ - | CONFIG_SYS_LBC_LSDMR_ACTTORW3 \ - | CONFIG_SYS_LBC_LSDMR_BL8 \ - | CONFIG_SYS_LBC_LSDMR_WRC3 \ - | CONFIG_SYS_LBC_LSDMR_CL3 \ +#define CONFIG_SYS_LBC_LSDMR_COMMON ( LSDMR_RFEN \ + | LSDMR_BSMA1516 \ + | LSDMR_RFCR8 \ + | LSDMR_PRETOACT6 \ + | LSDMR_ACTTORW3 \ + | LSDMR_BL8 \ + | LSDMR_WRC3 \ + | LSDMR_CL3 \ ) /* * SDRAM Controller configuration sequence. */ -#define CONFIG_SYS_LBC_LSDMR_1 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_PCHALL) -#define CONFIG_SYS_LBC_LSDMR_2 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_3 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_ARFRSH) -#define CONFIG_SYS_LBC_LSDMR_4 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_MRW) -#define CONFIG_SYS_LBC_LSDMR_5 ( CONFIG_SYS_LBC_LSDMR_COMMON \ - | CONFIG_SYS_LBC_LSDMR_OP_NORMAL) +#define CONFIG_SYS_LBC_LSDMR_1 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_PCHALL) +#define CONFIG_SYS_LBC_LSDMR_2 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_3 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_ARFRSH) +#define CONFIG_SYS_LBC_LSDMR_4 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_MRW) +#define CONFIG_SYS_LBC_LSDMR_5 (CONFIG_SYS_LBC_LSDMR_COMMON | LSDMR_OP_NORMAL) #endif /* * Serial Port */ #define CONFIG_CONS_INDEX 1 -#undef CONFIG_SERIAL_SOFTWARE_FIFO #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 @@ -335,6 +312,7 @@ #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR+0x4600) #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ /* Use the HUSH parser */ #define CONFIG_SYS_HUSH_PARSER #ifdef CONFIG_SYS_HUSH_PARSER @@ -351,7 +329,6 @@ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CONFIG_FSL_I2C #define CONFIG_I2C_MULTI_BUS -#define CONFIG_I2C_CMD_TREE #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ #define CONFIG_SYS_I2C_SLAVE 0x7F #define CONFIG_SYS_I2C_NOPROBES {{0,0x69}} /* Don't probe these addrs */ @@ -409,9 +386,7 @@ #undef PCI_ONE_PCI1 #endif -#define CONFIG_NET_MULTI #define CONFIG_PCI_PNP /* do pci plug-and-play */ -#define CONFIG_83XX_GENERIC_PCI #define CONFIG_83XX_PCI_STREAMING #undef CONFIG_EEPRO100 @@ -434,9 +409,6 @@ #define CONFIG_TSEC_ENET /* TSEC ethernet support */ #if defined(CONFIG_TSEC_ENET) -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif #define CONFIG_GMII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 @@ -536,10 +508,10 @@ /* * For booting Linux, the board info and command line data - * have to be in the first 8 MB of memory, since this is + * have to be in the first 256 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ +#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* Initial Memory map for Linux*/ #define CONFIG_SYS_RCWH_PCIHOST 0x80000000 /* PCIHOST */ @@ -634,11 +606,12 @@ #define CONFIG_SYS_SCCR_TSEC2CM 1 /* TSEC2 & I2C0 clock mode (0-3) */ /* System IO Config */ -#define CONFIG_SYS_SICRH SICRH_TSOBI1 +#define CONFIG_SYS_SICRH 0 #define CONFIG_SYS_SICRL SICRL_LDP_A #define CONFIG_SYS_HID0_INIT 0x000000000 -#define CONFIG_SYS_HID0_FINAL HID0_ENABLE_MACHINE_CHECK +#define CONFIG_SYS_HID0_FINAL (HID0_ENABLE_MACHINE_CHECK | \ + HID0_ENABLE_INSTRUCTION_CACHE) /* #define CONFIG_SYS_HID0_FINAL (\ HID0_ENABLE_INSTRUCTION_CACHE |\ @@ -683,7 +656,8 @@ #define CONFIG_SYS_IBAT5U (CONFIG_SYS_IMMR | BATU_BL_256M | BATU_VS | BATU_VP) /* SDRAM @ 0xF0000000, stack in DCACHE 0xFDF00000 & FLASH @ 0xFE000000 */ -#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE) +#define CONFIG_SYS_IBAT6L (0xF0000000 | BATL_PP_10 | BATL_MEMCOHERENCE | \ + BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT6U (0xF0000000 | BATU_BL_256M | BATU_VS | BATU_VP) #define CONFIG_SYS_IBAT7L (0) @@ -706,14 +680,6 @@ #define CONFIG_SYS_DBAT7L CONFIG_SYS_IBAT7L #define CONFIG_SYS_DBAT7U CONFIG_SYS_IBAT7U -/* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - #if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed of kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ @@ -725,23 +691,15 @@ #define CONFIG_ENV_OVERWRITE #if defined(CONFIG_TSEC_ENET) -#define CONFIG_ETHADDR 00:04:9f:ef:23:33 #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH0 -#define CONFIG_ETH1ADDR 00:E0:0C:00:7E:21 #endif -#define CONFIG_IPADDR 192.168.1.253 - #define CONFIG_HOSTNAME mpc8349emds #define CONFIG_ROOTPATH /nfsroot/rootfs #define CONFIG_BOOTFILE uImage -#define CONFIG_SERVERIP 192.168.1.1 -#define CONFIG_GATEWAYIP 192.168.1.1 -#define CONFIG_NETMASK 255.255.255.0 - -#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 800000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY 6 /* -1 disables auto-boot */ #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ @@ -772,8 +730,8 @@ "update=protect off fe000000 fe03ffff; " \ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ "upd=run load update\0" \ - "fdtaddr=400000\0" \ - "fdtfile=mpc8349emds.dtb\0" \ + "fdtaddr=780000\0" \ + "fdtfile=mpc834x_mds.dtb\0" \ "" #define CONFIG_NFSBOOTCOMMAND \