X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8313ERDB.h;h=6eec240e9f0b6f9e9563a90ecca60cc44adf994c;hb=cfd60441d8360cb9ffa315ecf3a2aef9bc134905;hp=6568fe13b85b5743db8823bf4a24ead7cc00bf67;hpb=1d1ab638f8b5961e4972d29394e573afb39667be;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 6568fe1..6eec240 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -38,6 +38,14 @@ #define CONFIG_PCI #define CONFIG_83XX_GENERIC_PCI +#define CONFIG_MISC_INIT_R + +/* + * On-board devices + */ +#define CONFIG_VSC7385_ENET + + #ifdef CFG_66MHZ #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ #elif defined(CFG_33MHZ) @@ -65,6 +73,22 @@ #define CFG_ACR_RPTCNT 3 /* Arbiter repeat count (0-7) */ /* + * Device configurations + */ + +/* Vitesse 7385 */ + +#ifdef CONFIG_VSC7385_ENET + +#define CONFIG_TSEC2 + +/* The flash address and size of the VSC7385 firmware image */ +#define CONFIG_VSC7385_IMAGE 0xFE7FE000 +#define CONFIG_VSC7385_IMAGE_SIZE 8192 + +#endif + +/* * DDR Setup */ #define CFG_DDR_BASE 0x00000000 /* DDR is system memory*/ @@ -76,10 +100,10 @@ * seem to have the SPD connected to I2C. */ #define CFG_DDR_SIZE 128 /* MB */ -#define CFG_DDR_CONFIG ( CSCONFIG_EN | CSCONFIG_AP \ - | 0x00040000 /* TODO */ \ +#define CFG_DDR_CONFIG ( CSCONFIG_EN \ + | 0x00010000 /* TODO */ \ | CSCONFIG_ROW_BIT_13 | CSCONFIG_COL_BIT_10 ) - /* 0x80840102 */ + /* 0x80010102 */ #define CFG_DDR_TIMING_3 0x00000000 #define CFG_DDR_TIMING_0 ( ( 0 << TIMING_CFG0_RWT_SHIFT ) \ @@ -92,25 +116,25 @@ | ( 2 << TIMING_CFG0_MRS_CYC_SHIFT ) ) /* 0x00220802 */ #define CFG_DDR_TIMING_1 ( ( 3 << TIMING_CFG1_PRETOACT_SHIFT ) \ - | ( 9 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ + | ( 8 << TIMING_CFG1_ACTTOPRE_SHIFT ) \ | ( 3 << TIMING_CFG1_ACTTORW_SHIFT ) \ | ( 5 << TIMING_CFG1_CASLAT_SHIFT ) \ - | (13 << TIMING_CFG1_REFREC_SHIFT ) \ + | (10 << TIMING_CFG1_REFREC_SHIFT ) \ | ( 3 << TIMING_CFG1_WRREC_SHIFT ) \ | ( 2 << TIMING_CFG1_ACTTOACT_SHIFT ) \ | ( 2 << TIMING_CFG1_WRTORD_SHIFT ) ) - /* 0x3935d322 */ -#define CFG_DDR_TIMING_2 ( ( 0 << TIMING_CFG2_ADD_LAT_SHIFT ) \ - | (31 << TIMING_CFG2_CPO_SHIFT ) \ + /* 0x3835a322 */ +#define CFG_DDR_TIMING_2 ( ( 1 << TIMING_CFG2_ADD_LAT_SHIFT ) \ + | ( 5 << TIMING_CFG2_CPO_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_LAT_DELAY_SHIFT ) \ | ( 2 << TIMING_CFG2_RD_TO_PRE_SHIFT ) \ | ( 2 << TIMING_CFG2_WR_DATA_DELAY_SHIFT ) \ | ( 3 << TIMING_CFG2_CKE_PLS_SHIFT ) \ - | (10 << TIMING_CFG2_FOUR_ACT_SHIFT) ) - /* 0x0f9048ca */ /* P9-45,may need tuning */ -#define CFG_DDR_INTERVAL ( ( 800 << SDRAM_INTERVAL_REFINT_SHIFT ) \ - | ( 100 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) - /* 0x03200064 */ + | ( 6 << TIMING_CFG2_FOUR_ACT_SHIFT) ) + /* 0x129048c6 */ /* P9-45,may need tuning */ +#define CFG_DDR_INTERVAL ( ( 1296 << SDRAM_INTERVAL_REFINT_SHIFT ) \ + | ( 1280 << SDRAM_INTERVAL_BSTOPRE_SHIFT ) ) + /* 0x05100500 */ #if defined(CONFIG_DDR_2T_TIMING) #define CFG_SDRAM_CFG ( SDRAM_CFG_SREN \ | SDRAM_CFG_SDRAM_TYPE_DDR2 \ @@ -124,9 +148,9 @@ #endif #define CFG_SDRAM_CFG2 0x00401000; /* set burst length to 8 for 32-bit data path */ -#define CFG_DDR_MODE ( ( 0x4440 << SDRAM_MODE_ESD_SHIFT ) \ - | ( 0x0232 << SDRAM_MODE_SD_SHIFT ) ) - /* 0x44400232 */ +#define CFG_DDR_MODE ( ( 0x4448 << SDRAM_MODE_ESD_SHIFT ) \ + | ( 0x0632 << SDRAM_MODE_SD_SHIFT ) ) + /* 0x44480632 */ #define CFG_DDR_MODE_2 0x8000C000; #define CFG_DDR_CLK_CNTL DDR_SDRAM_CLK_CNTL_CLK_ADJUST_05 @@ -178,6 +202,7 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +/* CFG_MONITOR_LEN must be a multiple of CFG_ENV_SECT_SIZE */ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ @@ -191,7 +216,7 @@ #define CFG_LBC_MRTPR 0x20000000 /*TODO */ /* LB refresh timer prescal, 266MHz/32 */ -/* drivers/nand/nand.c */ +/* drivers/mtd/nand/nand.c */ #define CFG_NAND_BASE 0xE2800000 /* 0xF0000000 */ #define CFG_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 @@ -213,28 +238,29 @@ #define CFG_LBLAWBAR1_PRELIM CFG_NAND_BASE #define CFG_LBLAWAR1_PRELIM 0x8000000E /* 32KB */ +/* local bus read write buffer mapping */ +#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ +#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ +#define CFG_LBLAWBAR3_PRELIM 0xFA000000 +#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ + +/* Vitesse 7385 */ + #define CFG_VSC7385_BASE 0xF0000000 -#define CONFIG_VSC7385_ENET /* VSC7385 ethernet support */ +#ifdef CONFIG_VSC7385_ENET + #define CFG_BR2_PRELIM 0xf0000801 /* VSC7385 Base address */ #define CFG_OR2_PRELIM 0xfffe09ff /* VSC7385, 128K bytes*/ #define CFG_LBLAWBAR2_PRELIM CFG_VSC7385_BASE/* Access window base at VSC7385 base */ #define CFG_LBLAWAR2_PRELIM 0x80000010 /* Access window size 128K */ -/* local bus read write buffer mapping */ -#define CFG_BR3_PRELIM 0xFA000801 /* map at 0xFA000000 */ -#define CFG_OR3_PRELIM 0xFFFF8FF7 /* 32kB */ -#define CFG_LBLAWBAR3_PRELIM 0xFA000000 -#define CFG_LBLAWAR3_PRELIM 0x8000000E /* 32KB */ +#endif /* pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 - -#define OF_CPU "PowerPC,8313@0" -#define OF_SOC "soc8313@e0000000" -#define OF_TBCLK (bd->bi_busfreq / 4) -#define OF_STDOUT_PATH "/soc8313@e0000000/serial@4500" +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* * Serial Port @@ -266,13 +292,6 @@ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 -/* TSEC */ -#define CFG_TSEC1_OFFSET 0x24000 -#define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) -#define CFG_TSEC2_OFFSET 0x25000 -#define CFG_TSEC2 (CFG_IMMR+CFG_TSEC2_OFFSET) -#define CONFIG_NET_MULTI - /* * General PCI * Addresses are mapped 1-1. @@ -291,26 +310,31 @@ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ /* - * TSEC configuration + * TSEC */ #define CONFIG_TSEC_ENET /* TSEC ethernet support */ -#ifndef CONFIG_NET_MULTI -#define CONFIG_NET_MULTI 1 -#endif - -#define CONFIG_GMII 1 /* MII PHY management */ -#define CONFIG_TSEC1 1 +#define CONFIG_NET_MULTI +#define CONFIG_GMII /* MII PHY management */ +#ifdef CONFIG_TSEC1 +#define CONFIG_HAS_ETH0 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 +#define CFG_TSEC1_OFFSET 0x24000 +#define TSEC1_PHY_ADDR 0x1c +#define TSEC1_FLAGS TSEC_GIGABIT +#define TSEC1_PHYIDX 0 +#endif + +#ifdef CONFIG_TSEC2 +#define CONFIG_HAS_ETH1 #define CONFIG_TSEC2_NAME "TSEC1" -#define TSEC1_PHY_ADDR 0x1c -#define TSEC2_PHY_ADDR 4 -#define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT -#define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 +#define CFG_TSEC2_OFFSET 0x25000 +#define TSEC2_PHY_ADDR 4 +#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC2_PHYIDX 0 +#endif + /* Options are: TSEC[0-1] */ #define CONFIG_ETHPRIME "TSEC1" @@ -326,7 +350,7 @@ */ #ifndef CFG_RAMBOOT #define CFG_ENV_IS_IN_FLASH 1 - #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x40000) + #define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) #define CFG_ENV_SECT_SIZE 0x10000 /* 64K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 @@ -389,11 +413,6 @@ */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux*/ -/* Cache Configuration */ -#define CFG_DCACHE_SIZE 16384 -#define CFG_CACHELINE_SIZE 32 -#define CFG_CACHELINE_SHIFT 5 /*log base 2 of the above value*/ - #define CFG_RCWH_PCIHOST 0x80000000 /* PCIHOST */ #ifdef CFG_66MHZ @@ -504,10 +523,13 @@ */ #define CONFIG_ENV_OVERWRITE +#ifdef CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:95:01 -#define CONFIG_HAS_ETH1 -#define CONFIG_HAS_ETH0 +#endif + +#ifdef CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 +#endif #define CONFIG_IPADDR 10.0.0.2 #define CONFIG_SERVERIP 10.0.0.1 @@ -521,7 +543,7 @@ #define CONFIG_UBOOTPATH u-boot.bin /* U-Boot image on TFTP server */ #define CONFIG_FDTFILE mpc8313erdb.dtb -#define CONFIG_LOADADDR 200000 /* default location for tftp and bootm */ +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ #define CONFIG_BOOTDELAY -1 /* -1 disables auto-boot */ #define CONFIG_BAUDRATE 115200