X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8260ADS.h;h=c312b7781dd7ba73196c2e6c309453f74aeb6547;hb=842033e6964e9e5d34aca893c1845416dd8ac2cc;hp=42fbe90a486c7c2b35ee0e29349a7e86b0fa2605;hpb=156feb90d200f186cdfd856d7f6f1878bb1bec1e;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 42fbe90..c312b77 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -17,6 +17,8 @@ * Vitaly Bordug * Added support for PCI bridge on MPC8272ADS * + * Copyright (C) Freescale Semiconductor, Inc. 2006-2009. + * * See file CREDITS for list of people who contributed to this * project. * @@ -46,12 +48,16 @@ #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xFFF00000 /* Standard: boot high */ +#endif + #define CONFIG_CPM2 1 /* Has a CPM2 */ /* * Figure out if we are booting low via flash HRCW or high via the BCSR. */ -#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ +#if (CONFIG_SYS_TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ # define CONFIG_SYS_LOWBOOT 1 #endif @@ -67,11 +73,19 @@ #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS #define CONFIG_MPC8272 1 +#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS +/* + * Actually MPC8275, but the code is littered with ifdefs that + * apply to both, or which use this ifdef to assume board-specific + * details. :-( + */ +#define CONFIG_MPC8272 1 #else #define CONFIG_MPC8260 1 #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */ /* allow serial and ethaddr to be overwritten */ #define CONFIG_ENV_OVERWRITE @@ -114,20 +128,20 @@ #if CONFIG_ETHER_INDEX == 1 # define CONFIG_SYS_PHY_ADDR 0 -# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) -# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +# define CONFIG_SYS_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK10) +# define CONFIG_SYS_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) #elif CONFIG_ETHER_INDEX == 2 #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS /* RxCLK is CLK15, TxCLK is CLK16 */ # define CONFIG_SYS_PHY_ADDR 3 -# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) +# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK15 | CMXFCR_TF2CS_CLK16) #else /* RxCLK is CLK13, TxCLK is CLK14 */ # define CONFIG_SYS_PHY_ADDR 0 -# define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) +# define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) #endif /* CONFIG_ADSTYPE == CONFIG_SYS_8272ADS */ -# define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +# define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) #endif /* CONFIG_ETHER_INDEX */ @@ -140,6 +154,9 @@ * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 2 /* Port C */ +#define MDIO_DECLARE volatile ioport_t *iop = ioport_addr ( \ + (immap_t *) CONFIG_SYS_IMMR, MDIO_PORT ) +#define MDC_DECLARE MDIO_DECLARE #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS #define CONFIG_SYS_MDIO_PIN 0x00002000 /* PC18 */ @@ -176,8 +193,9 @@ #endif /* CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS */ /*PCI*/ -#ifdef CONFIG_MPC8272 +#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS #define CONFIG_PCI +#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCI_PNP #define CONFIG_PCI_BOOTDELAY 0 #define CONFIG_PCI_SCAN_SHOW @@ -200,7 +218,6 @@ #define CONFIG_OF_LIBFDT 1 #define CONFIG_OF_BOARD_SETUP 1 #if defined(CONFIG_OF_LIBFDT) -#define OF_CPU "cpu@0" #define OF_TBCLK (bd->bi_busfreq / 4) #endif @@ -244,7 +261,6 @@ #elif CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS #undef CONFIG_CMD_SDRAM #undef CONFIG_CMD_I2C - #undef CONFIG_CMD_PCI #else #undef CONFIG_CMD_PCI @@ -271,7 +287,6 @@ * Miscellaneous configurable options */ #define CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #if defined(CONFIG_CMD_KGDB) @@ -318,7 +333,7 @@ #define CONFIG_SYS_IMMR 0xF0000000 #define CONFIG_SYS_BCSR 0xF4500000 -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS +#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS #define CONFIG_SYS_PCI_INT 0xF8200000 #endif #define CONFIG_SYS_SDRAM_BASE 0x00000000 @@ -333,9 +348,8 @@ #define BCSR_PCI_MODE 0x01000000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR -#define CONFIG_SYS_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in DPRAM */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET #ifdef CONFIG_SYS_LOWBOOT @@ -362,10 +376,8 @@ #define CONFIG_SYS_HRCW_SLAVE6 0 #define CONFIG_SYS_HRCW_SLAVE7 0 -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) # define CONFIG_SYS_RAMBOOT #endif @@ -413,6 +425,9 @@ #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ #define CONFIG_SYS_OR3_PRELIM 0xFFFF8010 +#elif CONFIG_ADSTYPE == CONFIG_SYS_PQ2FADS +#define CONFIG_SYS_BR8_PRELIM (CONFIG_SYS_PCI_INT | 0x1801) /* PCI interrupt controller */ +#define CONFIG_SYS_OR8_PRELIM 0xFFFF8010 #endif #define CONFIG_SYS_RMR RMR_CSRE @@ -447,7 +462,7 @@ #define CONFIG_SYS_RESET_ADDRESS 0x04400000 -#if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS +#if CONFIG_ADSTYPE >= CONFIG_SYS_PQ2FADS /* PCI Memory map (if different from default map */ #define CONFIG_SYS_PCI_SLV_MEM_LOCAL CONFIG_SYS_SDRAM_BASE /* Local base */ @@ -508,8 +523,48 @@ #endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ +#define CONFIG_HAS_ETH0 + #if CONFIG_ADSTYPE == CONFIG_SYS_8272ADS #define CONFIG_HAS_ETH1 #endif +#define CONFIG_NETDEV eth0 +#define CONFIG_LOADADDR 500000 /* default location for tftp and bootm */ + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=" __stringify(CONFIG_NETDEV) "\0" \ + "tftpflash=tftpboot $loadaddr $uboot; " \ + "protect off " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "erase " __stringify(CONFIG_SYS_TEXT_BASE) " +$filesize; " \ + "cp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize; " \ + "protect on " __stringify(CONFIG_SYS_TEXT_BASE) \ + " +$filesize; " \ + "cmp.b $loadaddr " __stringify(CONFIG_SYS_TEXT_BASE) \ + " $filesize\0" \ + "fdtaddr=400000\0" \ + "console=ttyCPM0\0" \ + "setbootargs=setenv bootargs " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" \ + "setipargs=setenv bootargs nfsroot=$serverip:$rootpath " \ + "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:$netdev:off " \ + "root=$rootdev rw console=$console,$baudrate $othbootargs\0" + +#define CONFIG_NFSBOOTCOMMAND \ + "setenv rootdev /dev/nfs;" \ + "run setipargs;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr - $fdtaddr" + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv rootdev /dev/ram;" \ + "run setbootargs;" \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + #endif /* __CONFIG_H */