X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMPC8260ADS.h;h=735cfaae5be33f6f0ff3da21442d401e2804842c;hb=9314cee6917444ab88bd4e758da7a30975120187;hp=626f23b6a436c28ab32f3446c4ea146183e38bf4;hpb=48abe7bfab14c1e9bd4a9a1f9d2e094b6d16773c;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MPC8260ADS.h b/include/configs/MPC8260ADS.h index 626f23b..735cfaa 100644 --- a/include/configs/MPC8260ADS.h +++ b/include/configs/MPC8260ADS.h @@ -13,6 +13,10 @@ * Ported to PQ2FADS-ZU and PQ2FADS-VR boards. * Ported to MPC8272ADS board. * + * Copyright (c) 2005 MontaVista Software, Inc. + * Vitaly Bordug + * Added support for PCI bridge on MPC8272ADS + * * See file CREDITS for list of people who contributed to this * project. * @@ -42,6 +46,15 @@ #define CONFIG_MPC8260ADS 1 /* Motorola PQ2 ADS family board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* + * Figure out if we are booting low via flash HRCW or high via the BCSR. + */ +#if (TEXT_BASE != 0xFFF00000) /* Boot low (flash HRCW) */ +# define CFG_LOWBOOT 1 +#endif + /* ADS flavours */ #define CFG_8260ADS 1 /* MPC8260ADS */ #define CFG_8266ADS 2 /* MPC8266ADS */ @@ -88,8 +101,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -133,7 +145,7 @@ #define CFG_MDIO_PIN 0x00002000 /* PC18 */ #define CFG_MDC_PIN 0x00001000 /* PC19 */ #else -#define CFG_MDIO_PIN 0x00400000 /* PC9 */ +#define CFG_MDIO_PIN 0x00400000 /* PC9 */ #define CFG_MDC_PIN 0x00200000 /* PC10 */ #endif /* CONFIG_ADSTYPE == CFG_8272ADS */ @@ -159,12 +171,20 @@ #define CFG_I2C_SLAVE 0x7F #if defined(CONFIG_SPD_EEPROM) && !defined(CONFIG_SPD_ADDR) -#define CONFIG_SPD_ADDR 0x50 +#define CONFIG_SPD_ADDR 0x50 #endif #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ +/*PCI*/ +#ifdef CONFIG_MPC8272 +#define CONFIG_PCI +#define CONFIG_PCI_PNP +#define CONFIG_PCI_BOOTDELAY 0 +#define CONFIG_PCI_SCAN_SHOW +#endif + #ifndef CONFIG_SDRAM_PBI -#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ +#define CONFIG_SDRAM_PBI 0 /* By default, use bank-based interleaving */ #endif #ifndef CONFIG_8260_CLKIN @@ -175,51 +195,68 @@ #endif #endif -#define CONFIG_BAUDRATE 38400 - -#define CFG_EXCLUDE CFG_CMD_BEDBUG | \ - CFG_CMD_BMP | \ - CFG_CMD_BSP | \ - CFG_CMD_DATE | \ - CFG_CMD_DOC | \ - CFG_CMD_DTT | \ - CFG_CMD_EEPROM | \ - CFG_CMD_ELF | \ - CFG_CMD_FAT | \ - CFG_CMD_FDC | \ - CFG_CMD_FDOS | \ - CFG_CMD_HWFLOW | \ - CFG_CMD_IDE | \ - CFG_CMD_KGDB | \ - CFG_CMD_MMC | \ - CFG_CMD_NAND | \ - CFG_CMD_PCI | \ - CFG_CMD_PCMCIA | \ - CFG_CMD_REISER | \ - CFG_CMD_SCSI | \ - CFG_CMD_SPI | \ - CFG_CMD_USB | \ - CFG_CMD_VFD | \ - CFG_CMD_XIMG +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#if defined(CONFIG_OF_LIBFDT) +#define OF_CPU "cpu@0" +#define OF_TBCLK (bd->bi_busfreq / 4) +#endif + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_CDP +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_PORTIO +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_SDRAM + +#undef CONFIG_CMD_XIMG + +#if CONFIG_ADSTYPE == CFG_8272ADS + #undef CONFIG_CMD_SDRAM + #undef CONFIG_CMD_I2C + +#elif CONFIG_ADSTYPE >= CFG_PQ2FADS + #undef CONFIG_CMD_SDRAM + #undef CONFIG_CMD_I2C + #undef CONFIG_CMD_PCI -#if CONFIG_ADSTYPE >= CFG_PQ2FADS -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_CMD_SDRAM | \ - CFG_CMD_I2C | \ - CFG_EXCLUDE ) ) #else -#define CONFIG_COMMANDS (CFG_CMD_ALL & ~( \ - CFG_EXCLUDE ) ) + #undef CONFIG_CMD_PCI + #endif /* CONFIG_ADSTYPE >= CFG_PQ2FADS */ -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ #define CONFIG_BOOTCOMMAND "bootm fff80000" /* autoboot command */ #define CONFIG_BOOTARGS "root=/dev/mtdblock2" -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #undef CONFIG_KGDB_ON_SMC /* define if kgdb on SMC */ #define CONFIG_KGDB_ON_SCC /* define if kgdb on SCC */ #undef CONFIG_KGDB_NONE /* define if kgdb on something else */ @@ -228,7 +265,7 @@ #endif #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ -#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ /* * Miscellaneous configurable options @@ -237,7 +274,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -249,7 +286,7 @@ #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ -#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_LOAD_ADDR 0x400000 /* default load address */ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ @@ -265,16 +302,25 @@ #define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */ #define CFG_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ -#define CFG_JFFS2_FIRST_SECTOR 1 -#define CFG_JFFS2_LAST_SECTOR 27 +/* + * JFFS2 partitions + * + * Note: fake mtd_id used, no linux mtd map file + */ +#define MTDIDS_DEFAULT "nor0=mpc8260ads-0" +#define MTDPARTS_DEFAULT "mtdparts=mpc8260ads-0:-@1m(jffs2)" #define CFG_JFFS2_SORT_FRAGMENTS -#define CFG_JFFS_CUSTOM_PART /* this is stuff came out of the Motorola docs */ +#ifndef CFG_LOWBOOT #define CFG_DEFAULT_IMMR 0x0F010000 +#endif #define CFG_IMMR 0xF0000000 #define CFG_BCSR 0xF4500000 +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_PCI_INT 0xF8200000 +#endif #define CFG_SDRAM_BASE 0x00000000 #define CFG_LSDRAM_BASE 0xFD000000 @@ -292,13 +338,21 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET - -/* 0x0EA28205 */ +#ifdef CFG_LOWBOOT +/* PQ2FADS flash HRCW = 0x0EB4B645 */ +#define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ + ( HRCW_L2CPC10 | HRCW_DPPC11 | HRCW_ISB100 ) |\ + ( HRCW_BMS | HRCW_MMR11 | HRCW_LBPC01 | HRCW_APPC10 ) |\ + ( HRCW_CS10PC01 | HRCW_MODCK_H0101 ) \ + ) +#else +/* PQ2FADS BCSR HRCW = 0x0CB23645 */ #define CFG_HRCW_MASTER ( ( HRCW_BPS11 | HRCW_CIP ) |\ ( HRCW_L2CPC10 | HRCW_DPPC10 | HRCW_ISB010 ) |\ ( HRCW_BMS | HRCW_APPC10 ) |\ ( HRCW_MODCK_H0101 ) \ ) +#endif /* no slaves */ #define CFG_HRCW_SLAVE1 0 #define CFG_HRCW_SLAVE2 0 @@ -330,18 +384,16 @@ # define CFG_ENV_SECT_SIZE 0x40000 # define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_ENV_SECT_SIZE) #else -# define CFG_ENV_IS_IN_NVRAM 1 +# define CONFIG_ENV_IS_IN_NVRAM 1 # define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) # define CFG_ENV_SIZE 0x200 #endif /* CFG_RAMBOOT */ - #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif - #define CFG_HID0_INIT 0 #define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE ) @@ -351,11 +403,18 @@ #define CFG_BCR 0x100C0000 #define CFG_SIUMCR 0x0A200000 #define CFG_SCCR SCCR_DFBRG01 -#define CFG_BR0_PRELIM CFG_FLASH_BASE | 0x00001801 +#define CFG_BR0_PRELIM (CFG_FLASH_BASE | 0x00001801) #define CFG_OR0_PRELIM 0xFF800876 -#define CFG_BR1_PRELIM CFG_BCSR | 0x00001801 +#define CFG_BR1_PRELIM (CFG_BCSR | 0x00001801) #define CFG_OR1_PRELIM 0xFFFF8010 +/*We need to configure chip select to use CPLD PCI IC on MPC8272ADS*/ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CFG_BR3_PRELIM (CFG_PCI_INT | 0x1801) /* PCI interrupt controller */ +#define CFG_OR3_PRELIM 0xFFFF8010 +#endif + #define CFG_RMR RMR_CSRE #define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) #define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) @@ -388,4 +447,69 @@ #define CFG_RESET_ADDRESS 0x04400000 +#if CONFIG_ADSTYPE == CFG_8272ADS + +/* PCI Memory map (if different from default map */ +#define CFG_PCI_SLV_MEM_LOCAL CFG_SDRAM_BASE /* Local base */ +#define CFG_PCI_SLV_MEM_BUS 0x00000000 /* PCI base */ +#define CFG_PICMR0_MASK_ATTRIB (PICMR_MASK_512MB | PICMR_ENABLE | \ + PICMR_PREFETCH_EN) + +/* + * These are the windows that allow the CPU to access PCI address space. + * All three PCI master windows, which allow the CPU to access PCI + * prefetch, non prefetch, and IO space (see below), must all fit within + * these windows. + */ + +/* + * Master window that allows the CPU to access PCI Memory (prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEM_LOCAL 0x80000000 /* Local base */ +#define CFG_PCI_MSTR_MEM_BUS 0x80000000 /* PCI base */ +#define CFG_CPU_PCI_MEM_START PCI_MSTR_MEM_LOCAL +#define CFG_PCI_MSTR_MEM_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR0_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE | POCMR_PREFETCH_EN) + +/* + * Master window that allows the CPU to access PCI Memory (non-prefetch). + * This window will be setup with the second set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_MEMIO_LOCAL 0xA0000000 /* Local base */ +#define CFG_PCI_MSTR_MEMIO_BUS 0xA0000000 /* PCI base */ +#define CFG_CPU_PCI_MEMIO_START PCI_MSTR_MEMIO_LOCAL +#define CFG_PCI_MSTR_MEMIO_SIZE 0x20000000 /* 512MB */ +#define CFG_POCMR1_MASK_ATTRIB (POCMR_MASK_512MB | POCMR_ENABLE) + +/* + * Master window that allows the CPU to access PCI IO space. + * This window will be setup with the first set of Outbound ATU registers + * in the bridge. + */ + +#define CFG_PCI_MSTR_IO_LOCAL 0xF6000000 /* Local base */ +#define CFG_PCI_MSTR_IO_BUS 0x00000000 /* PCI base */ +#define CFG_CPU_PCI_IO_START PCI_MSTR_IO_LOCAL +#define CFG_PCI_MSTR_IO_SIZE 0x02000000 /* 64MB */ +#define CFG_POCMR2_MASK_ATTRIB (POCMR_MASK_32MB | POCMR_ENABLE | POCMR_PCI_IO) + + +/* PCIBR0 - for PCI IO*/ +#define CFG_PCI_MSTR0_LOCAL CFG_PCI_MSTR_IO_LOCAL /* Local base */ +#define CFG_PCIMSK0_MASK ~(CFG_PCI_MSTR_IO_SIZE - 1U) /* Size of window */ +/* PCIBR1 - prefetch and non-prefetch regions joined together */ +#define CFG_PCI_MSTR1_LOCAL CFG_PCI_MSTR_MEM_LOCAL +#define CFG_PCIMSK1_MASK ~(CFG_PCI_MSTR_MEM_SIZE + CFG_PCI_MSTR_MEMIO_SIZE - 1U) + +#endif /* CONFIG_ADSTYPE == CONFIG_8272ADS*/ + +#if CONFIG_ADSTYPE == CFG_8272ADS +#define CONFIG_HAS_ETH1 +#endif + #endif /* __CONFIG_H */