X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMIP405.h;h=7ac934225191bd82eee64e564fdc11169170e84c;hb=a694610d3361465d4c8d27dde72ab8b63d31115e;hp=8d7930765acaa14941945087d0d9dc5ffc997f33;hpb=8bde7f776c77b343aca29b8c7b58464d915ac245;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MIP405.h b/include/configs/MIP405.h index 8d79307..7ac9342 100644 --- a/include/configs/MIP405.h +++ b/include/configs/MIP405.h @@ -50,42 +50,45 @@ ***********************************************************/ #define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */ -/*********************************************************** - * Command definitions - ***********************************************************/ -#define MIP405_COMMON_CMDS \ - (CONFIG_CMD_DFL | \ - CFG_CMD_IDE | \ - CFG_CMD_DHCP | \ - CFG_CMD_CACHE | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_ECHO | \ - CFG_CMD_EEPROM | \ - CFG_CMD_I2C | \ - CFG_CMD_REGINFO | \ - CFG_CMD_DATE | \ - CFG_CMD_ELF | \ - CFG_CMD_MII | \ - CFG_CMD_SAVES | \ - CFG_CMD_BSP ) -#if defined(CONFIG_MIP405T) -#define CONFIG_COMMANDS \ - MIP405_COMMON_CMDS -#else -#define CONFIG_COMMANDS \ - (MIP405_COMMON_CMDS | \ - CFG_CMD_USB | \ - CFG_CMD_DOC ) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_CACHE +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MII +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_BSP +#if !defined(CONFIG_MIP405T) + #define CONFIG_CMD_USB #endif -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include -#define CFG_HUSH_PARSER -#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " /************************************************************** * I2C Stuff: * the MIP405 is equiped with an Atmel 24C128/256 EEPROM at address @@ -94,30 +97,29 @@ ***************************************************************/ #define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CFG_I2C_SPEED 50000 /* I2C speed and slave address */ -#define CFG_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_SPEED 50000 /* I2C speed and slave address */ +#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CFG_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ -#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ +#define CONFIG_SYS_I2C_EEPROM_ADDR 0x53 /* EEPROM 24C128/256 */ +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ /* mask of address bits that overflow into the "EEPROM chip address" */ -#undef CFG_I2C_EEPROM_ADDR_OVERFLOW -#define CFG_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ +#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* The Atmel 24C128/256 has */ /* 64 byte page write mode using*/ /* last 6 bits of the address */ -#define CFG_EEPROM_PAGE_WRITE_ENABLE /* enable Page write */ -#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CFG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ -#define CFG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CONFIG_ENV_OFFSET 0x00000 /* environment starts at the beginning of the EEPROM */ +#define CONFIG_ENV_SIZE 0x00800 /* 2k bytes may be used for env vars */ /*************************************************************** * Definitions for Serial Presence Detect EEPROM address * (to get SDRAM settings) ***************************************************************/ /*#define SDRAM_EEPROM_WRITE_ADDRESS 0xA0 -#define SDRAM_EEPROM_READ_ADDRESS 0xA1 +#define SDRAM_EEPROM_READ_ADDRESS 0xA1 */ /************************************************************** * Environment definitions @@ -125,8 +127,8 @@ #define CONFIG_BAUDRATE 9600 /* STD Baudrate */ #define CONFIG_BOOTDELAY 5 /* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -#define CONFIG_BOOT_RETRY_TIME -10 /* feature is avaiable but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ #define CONFIG_BOOTCOMMAND "diskboot 400000 0:1; bootm" /* autoboot command */ #define CONFIG_BOOTARGS "console=ttyS0,9600 root=/dev/hda5" /* boot arguments */ @@ -137,54 +139,54 @@ /*************************************************************** * defines if the console is stored in the environment ***************************************************************/ -#define CFG_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV /* stdin, stdout and stderr are in evironment */ /*************************************************************** * defines if an overwrite_console function exists *************************************************************/ -#define CFG_CONSOLE_OVERWRITE_ROUTINE -#define CFG_CONSOLE_INFO_QUIET +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_SYS_CONSOLE_INFO_QUIET /*************************************************************** * defines if the overwrite_console should be stored in the * environment **************************************************************/ -#undef CFG_CONSOLE_ENV_OVERWRITE +#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE /************************************************************** * loads config *************************************************************/ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ #define CONFIG_MISC_INIT_R /*********************************************************** * Miscellaneous configurable options **********************************************************/ -#define CFG_LONGHELP /* undef to save memory */ -#define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ #else -#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ #endif -#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_MAXARGS 16 /* max number of command args */ -#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ -#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ -#define CFG_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x0100000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 1 ... 12 MB in DRAM */ -#undef CFG_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CFG_BASE_BAUD 916667 +#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ +#define CONFIG_SYS_BASE_BAUD 916667 /* The following table includes the supported baudrates */ -#define CFG_BAUDRATE_TABLE \ +#define CONFIG_SYS_BAUDRATE_TABLE \ { 300, 600, 1200, 2400, 4800, 9600, 19200, 38400, \ 57600, 115200, 230400, 460800, 921600 } -#define CFG_LOAD_ADDR 0x400000 /* default load address */ -#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ +#define CONFIG_SYS_LOAD_ADDR 0x400000 /* default load address */ +#define CONFIG_SYS_EXTBDINFO 1 /* To use extended board_into (bd_t) */ -#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ /*----------------------------------------------------------------------- * PCI stuff @@ -198,58 +200,87 @@ #define CONFIG_PCI_HOST PCI_HOST_FORCE /* configure as pci-host */ #define CONFIG_PCI_PNP /* pci plug-and-play */ /* resource configuration */ -#define CFG_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ -#define CFG_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ -#define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CFG_PCI_PTM2LA 0x00000000 /* disabled */ -#define CFG_PCI_PTM2MS 0x00000000 /* disabled */ -#define CFG_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x0000 /* PCI Vendor ID: to-do!!! */ +#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0000 /* PCI Device ID: to-do!!! */ +#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ +#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */ +#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ +#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */ +#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */ +#define CONFIG_SYS_PCI_PTM2PCI 0x00000000 /* Host: use this pci address */ /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) - * Please note that CFG_SDRAM_BASE _must_ start at 0 + * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ -#define CFG_SDRAM_BASE 0x00000000 -#define CFG_FLASH_BASE 0xFFF80000 -#define CFG_MONITOR_BASE CFG_FLASH_BASE -#define CFG_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserve 128 kB for malloc() */ +#define CONFIG_SYS_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_FLASH_BASE 0xFFF80000 +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Monitor */ +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* Reserve 1024 kB for malloc() */ /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is * the maximum mapped by the Linux kernel during initialization. */ -#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ /*----------------------------------------------------------------------- * FLASH organization */ -#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ +#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ -#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ -#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ +#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +/* + * JFFS2 partitions + * + */ +/* No command line, one static partition, whole device */ +#undef CONFIG_CMD_MTDPARTS +#define CONFIG_JFFS2_DEV "nor0" +#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF +#define CONFIG_JFFS2_PART_OFFSET 0x00000000 + +/* mtdparts command line support */ +/* Note: fake mtd_id used, no linux mtd map file */ +/* +#define CONFIG_CMD_MTDPARTS +#define MTDIDS_DEFAULT "nor0=mip405-0" +#define MTDPARTS_DEFAULT "mtdparts=mip405-0:-(jffs2)" +*/ /*----------------------------------------------------------------------- - * Cache Configuration + * Logbuffer Configuration */ -#define CFG_DCACHE_SIZE 0x4000 /* For IBM 405GPr CPUs */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif +#undef CONFIG_LOGBUFFER /* supported but not enabled */ +/*----------------------------------------------------------------------- + * Bootcountlimit Configuration + */ +#undef CONFIG_BOOTCOUNT_LIMIT /* supported but not enabled */ +/*----------------------------------------------------------------------- + * POST Configuration + */ +#if 0 /* enable this if POST is desired (is supported but not enabled) */ +#define CONFIG_POST (CONFIG_SYS_POST_MEMORY | \ + CONFIG_SYS_POST_CPU | \ + CONFIG_SYS_POST_RTC | \ + CONFIG_SYS_POST_I2C) + +#endif /* * Init Memory Controller: */ +#define FLASH_MAX_SIZE 0x00800000 /* 8MByte max */ +#define FLASH_BASE_PRELIM 0xFF800000 /* open the flash CS */ +/* Size: 0=1MB, 1=2MB, 2=4MB, 3=8MB, 4=16MB, 5=32MB, 6=64MB, 7=128MB */ +#define FLASH_SIZE_PRELIM 3 /* maximal flash FLASH size bank #0 */ -#define FLASH_BASE0_PRELIM 0xFFC00000 /* FLASH bank #0 */ -#define FLASH_BASE1_PRELIM 0 /* FLASH bank #1 */ - -#define CONFIG_BOARD_PRE_INIT +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Peripheral Bus Mapping */ #define PER_PLD_ADDR 0xF4000000 /* smallest window is 1MByte 0x10 0000*/ @@ -257,20 +288,29 @@ #define PER_UART1_ADDR 0xF4200000 /* smallest window is 1MByte 0x10 0000*/ #define MULTI_PURPOSE_SOCKET_ADDR 0xF8000000 -#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 +#define CONFIG_PORT_ADDR PER_PLD_ADDR + 5 /*----------------------------------------------------------------------- * Definitions for initial stack pointer and data area (in On Chip SRAM) */ -#define CFG_TEMP_STACK_OCM 1 -#define CFG_OCM_DATA_ADDR 0xF0000000 -#define CFG_OCM_DATA_SIZE 0x1000 -#define CFG_INIT_RAM_ADDR CFG_OCM_DATA_ADDR /* inside of On Chip SRAM */ -#define CFG_INIT_RAM_END CFG_OCM_DATA_SIZE /* End of On Chip SRAM */ -#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ -#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) -#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET +#define CONFIG_SYS_TEMP_STACK_OCM 1 +#define CONFIG_SYS_OCM_DATA_ADDR 0xF0000000 +#define CONFIG_SYS_OCM_DATA_SIZE 0x1000 +#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of On Chip SRAM */ +#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of On Chip SRAM */ +#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +/* reserve some memory for POST and BOOT limit info */ +#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 32) + +#ifdef CONFIG_POST /* reserve one word for POST Info */ +#define CONFIG_SYS_POST_WORD_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 4) +#endif + +#ifdef CONFIG_BOOTCOUNT_LIMIT /* reserve 2 word for bootcount limit */ +#define CONFIG_SYS_BOOTCOUNT_ADDR (CONFIG_SYS_GBL_DATA_OFFSET - 12) +#endif /* * Internal Definitions @@ -284,7 +324,7 @@ /*********************************************************************** * External peripheral base address ***********************************************************************/ -#define CFG_ISA_IO_BASE_ADDRESS 0xE8000000 +#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0xE8000000 /*********************************************************************** * Last Stage Init @@ -293,9 +333,12 @@ /************************************************************ * Ethernet Stuff ***********************************************************/ +#define CONFIG_PPC4xx_EMAC #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ - +#define CONFIG_PHY_RESET_DELAY 300 /* Intel LXT971A needs this */ +#define CONFIG_PHY_CMD_DELAY 40 /* Intel LXT971A needs this */ +#define CONFIG_NET_MULTI /************************************************************ * RTC ***********************************************************/ @@ -306,42 +349,31 @@ * IDE/ATA stuff ************************************************************/ #if defined(CONFIG_MIP405T) -#define CFG_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ +#define CONFIG_SYS_IDE_MAXBUS 1 /* MIP405T has only one IDE bus */ #else -#define CFG_IDE_MAXBUS 2 /* max. 2 IDE busses */ +#define CONFIG_SYS_IDE_MAXBUS 2 /* max. 2 IDE busses */ #endif -#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ +#define CONFIG_SYS_IDE_MAXDEVICE (CONFIG_SYS_IDE_MAXBUS*2) /* max. 2 drives per IDE bus */ -#define CFG_ATA_BASE_ADDR CFG_ISA_IO_BASE_ADDRESS /* base address */ -#define CFG_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ -#define CFG_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ -#define CFG_ATA_DATA_OFFSET 0 /* data reg offset */ -#define CFG_ATA_REG_OFFSET 0 /* reg offset */ -#define CFG_ATA_ALT_OFFSET 0x200 /* alternate register offset */ +#define CONFIG_SYS_ATA_BASE_ADDR CONFIG_SYS_ISA_IO_BASE_ADDRESS /* base address */ +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x01F0 /* ide0 offste */ +#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0170 /* ide1 offset */ +#define CONFIG_SYS_ATA_DATA_OFFSET 0 /* data reg offset */ +#define CONFIG_SYS_ATA_REG_OFFSET 0 /* reg offset */ +#define CONFIG_SYS_ATA_ALT_OFFSET 0x200 /* alternate register offset */ #undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */ #undef CONFIG_IDE_LED /* no led for ide supported */ #define CONFIG_IDE_RESET /* reset for ide supported... */ #define CONFIG_IDE_RESET_ROUTINE /* with a special reset function */ - +#define CONFIG_SUPPORT_VFAT /************************************************************ * ATAPI support (experimental) ************************************************************/ #define CONFIG_ATAPI /* enable ATAPI Support */ /************************************************************ - * SCSI support (experimental) only SYM53C8xx supported - ************************************************************/ -#undef CONFIG_SCSI_SYM53C8XX - -#ifdef CONFIG_SCSI_SYM53C8XX -#define CFG_SCSI_MAX_LUN 8 /* number of supported LUNs */ -#define CFG_SCSI_MAX_SCSI_ID 7 /* maximum SCSI ID (0..6) */ -#define CFG_SCSI_MAX_DEVICE CFG_SCSI_MAX_SCSI_ID * CFG_SCSI_MAX_LUN /* maximum Target devices */ -#define CFG_SCSI_SPIN_UP_TIME 2 -#endif /* CONFIG_SCSI_SYM53C8XX */ -/************************************************************ * DISK Partition support ************************************************************/ #define CONFIG_DOS_PARTITION @@ -349,13 +381,6 @@ #define CONFIG_ISO_PARTITION /* Experimental */ /************************************************************ - * Disk-On-Chip configuration - ************************************************************/ -#define CFG_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ -#define CFG_DOC_SHORT_TIMEOUT -#define CFG_DOC_SUPPORT_2000 -#define CFG_DOC_SUPPORT_MILLENNIUM -/************************************************************ * Keyboard support ************************************************************/ #undef CONFIG_ISA_KEYBOARD @@ -380,17 +405,22 @@ #define CONFIG_USB_STORAGE /* Enable needed helper functions */ -#define CFG_DEVICE_DEREGISTER /* needs device_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ #endif /************************************************************ * Debug support ************************************************************/ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif /************************************************************ + * support BZIP2 compression + ************************************************************/ +#define CONFIG_BZIP2 1 + +/************************************************************ * Ident ************************************************************/