X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FMERGERBOX.h;h=3dcea0b595bc725e021dafc3e9ec9085f93dcf4c;hb=f763be224fa78893384416734419d8e052c1c5ef;hp=f9681cd1ab95a913e842f20350315b616451fea3;hpb=7fb3e7a2d64b902e423c9e5a3aedc1f4179ac27d;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/MERGERBOX.h b/include/configs/MERGERBOX.h index f9681cd..3dcea0b 100644 --- a/include/configs/MERGERBOX.h +++ b/include/configs/MERGERBOX.h @@ -4,20 +4,7 @@ * Copyright (C) 2011 Matrix Vision GmbH * Andre Schwarz * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef __CONFIG_H @@ -29,13 +16,13 @@ * High Level Configuration Options */ #define CONFIG_E300 1 -#define CONFIG_MPC83xx 1 #define CONFIG_MPC837x 1 #define CONFIG_MPC8377 1 #define CONFIG_SYS_TEXT_BASE 0xFC000000 #define CONFIG_PCI 1 +#define CONFIG_PCI_INDIRECT_BRIDGE 1 #define CONFIG_MASK_AER_AO #define CONFIG_DISPLAY_AER_FULL @@ -159,11 +146,13 @@ #define CONFIG_SYS_LBLAWBAR0_PRELIM CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_LBLAWAR0_PRELIM (LBLAWAR_EN | LBLAWAR_64MB) -#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 | BR_V) +#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | BR_PS_16 |\ + BR_MS_GPCM | BR_V) #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | OR_UPM_XAM |\ OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 |\ - OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_TRLX |\ - OR_GPCM_EHTR | OR_GPCM_EAD) + OR_GPCM_XACS | OR_GPCM_SCY_15 |\ + OR_GPCM_TRLX_SET | OR_GPCM_EHTR_SET |\ + OR_GPCM_EAD) #define CONFIG_SYS_MAX_FLASH_BANKS 1 #define CONFIG_SYS_MAX_FLASH_SECT 512 @@ -177,17 +166,17 @@ */ #define CONFIG_MTD_NAND_VERIFY_WRITE 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_NAND_FSL_ELBC 1 +#define CONFIG_NAND_FSL_ELBC 1 #define CONFIG_SYS_NAND_BASE 0xE0600000 -#define CONFIG_SYS_BR1_PRELIM (CONFIG_SYS_NAND_BASE | (2< " /* Pass open firmware flat tree */ #define CONFIG_OF_LIBFDT 1 @@ -222,13 +210,14 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1 /* I2C */ -#define CONFIG_HARD_I2C -#define CONFIG_FSL_I2C -#define CONFIG_I2C_MULTI_BUS -#define CONFIG_SYS_I2C_SPEED 120000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x3000 -#define CONFIG_SYS_I2C2_OFFSET 0x3100 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 400000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000 +#define CONFIG_SYS_FSL_I2C2_SPEED 400000 +#define CONFIG_SYS_FSL_I2C2_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C2_OFFSET 0x3100 /* * General PCI @@ -273,7 +262,6 @@ /* * TSEC */ -#define CONFIG_NET_MULTI #define CONFIG_GMII /* MII PHY management */ #define CONFIG_SYS_VSC8601_SKEWFIX #define CONFIG_SYS_VSC8601_SKEW_TX 3 @@ -372,13 +360,11 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_SYS_LOAD_ADDR 0x2000000 #define CONFIG_LOADADDR 0x4000000 -#define CONFIG_SYS_PROMPT "=> " #define CONFIG_SYS_CBSIZE 256 #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) #define CONFIG_SYS_MAXARGS 16 #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE -#define CONFIG_SYS_HZ 1000 #define CONFIG_LOADS_ECHO 1 #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 @@ -409,7 +395,7 @@ /* DDR: cache cacheable */ #define CONFIG_SYS_SDRAM CONFIG_SYS_SDRAM_BASE -#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT0L (CONFIG_SYS_SDRAM | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT0U (CONFIG_SYS_SDRAM | BATU_BL_256M | BATU_VS |\ BATU_VP) @@ -423,7 +409,7 @@ #define CONFIG_SYS_DBAT1U CONFIG_SYS_IBAT1U /* IMMRBAR, PCI IO and NAND: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT2L (CONFIG_SYS_IMMR | BATL_PP_RW |\ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT2U (CONFIG_SYS_IMMR | BATU_BL_8M | BATU_VS |\ BATU_VP) @@ -437,23 +423,23 @@ #define CONFIG_SYS_DBAT3U CONFIG_SYS_IBAT3U /* FLASH: icache cacheable, but dcache-inhibit and guarded */ -#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT4U (CONFIG_SYS_FLASH_BASE | BATU_BL_64M |\ BATU_VS | BATU_VP) -#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_10 | \ +#define CONFIG_SYS_DBAT4L (CONFIG_SYS_FLASH_BASE | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_DBAT4U CONFIG_SYS_IBAT4U /* Stack in dcache: cacheable, no memory coherence */ -#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_10) +#define CONFIG_SYS_IBAT5L (CONFIG_SYS_INIT_RAM_ADDR | BATL_PP_RW) #define CONFIG_SYS_IBAT5U (CONFIG_SYS_INIT_RAM_ADDR | BATU_BL_128K |\ BATU_VS | BATU_VP) #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U /* PCI MEM space: cacheable */ -#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_10 |\ +#define CONFIG_SYS_IBAT6L (CONFIG_SYS_PCI_MEM_PHYS | BATL_PP_RW |\ BATL_MEMCOHERENCE) #define CONFIG_SYS_IBAT6U (CONFIG_SYS_PCI_MEM_PHYS | BATU_BL_256M |\ BATU_VS | BATU_VP) @@ -461,7 +447,7 @@ #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U /* PCI MMIO space: cache-inhibit and guarded */ -#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_10 | \ +#define CONFIG_SYS_IBAT7L (CONFIG_SYS_PCI_MMIO_PHYS | BATL_PP_RW | \ BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) #define CONFIG_SYS_IBAT7U (CONFIG_SYS_PCI_MMIO_PHYS | BATU_BL_256M |\ BATU_VS | BATU_VP) @@ -474,7 +460,7 @@ #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10 -#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 #define CONFIG_SYS_EEPROM_SIZE 0x4000 /* @@ -531,8 +517,8 @@ #define CONFIG_ZERO_BOOTDELAY_CHECK #define CONFIG_RESET_TO_RETRY 1000 -#define MV_CI MergerBox -#define MV_VCI MergerBox +#define MV_CI "MergerBox" +#define MV_VCI "MergerBox" #define MV_FPGA_DATA 0xfc100000 #define MV_FPGA_SIZE 0x00200000 @@ -548,9 +534,6 @@ "then; run fitboot;else;run ubiboot;fi;" #define CONFIG_BOOTARGS "console=ttyS0,115200n8" -#define XMK_STR(x) #x -#define MK_STR(x) XMK_STR(x) - #define CONFIG_EXTRA_ENV_SETTINGS \ "console_nr=0\0"\ "stdin=serial\0"\ @@ -559,20 +542,20 @@ "boot_sqfs=1\0"\ "usb_dr_mode=host\0"\ "bootfile=MergerBox.fit\0"\ - "baudrate=" MK_STR(CONFIG_BAUDRATE) "\0"\ + "baudrate=" __stringify(CONFIG_BAUDRATE) "\0"\ "fpga=0\0"\ - "fpgadata=" MK_STR(MV_FPGA_DATA) "\0"\ - "fpgadatasize=" MK_STR(MV_FPGA_SIZE) "\0"\ - "mv_kernel_ram=" MK_STR(MV_KERNEL_ADDR_RAM) "\0"\ - "mv_initrd_ram=" MK_STR(MV_INITRD_ADDR_RAM) "\0"\ - "mv_dtb_ram=" MK_STR(MV_DTB_ADDR_RAM) "\0"\ - "uboota=" MK_STR(CONFIG_SYS_TEXT_BASE) "\0"\ - "fitaddr=" MK_STR(MV_FITADDR) "\0"\ + "fpgadata=" __stringify(MV_FPGA_DATA) "\0"\ + "fpgadatasize=" __stringify(MV_FPGA_SIZE) "\0"\ + "mv_kernel_ram=" __stringify(MV_KERNEL_ADDR_RAM) "\0"\ + "mv_initrd_ram=" __stringify(MV_INITRD_ADDR_RAM) "\0"\ + "mv_dtb_ram=" __stringify(MV_DTB_ADDR_RAM) "\0"\ + "uboota=" __stringify(CONFIG_SYS_TEXT_BASE) "\0"\ + "fitaddr=" __stringify(MV_FITADDR) "\0"\ "mv_version=" U_BOOT_VERSION "\0"\ "mtdids=" MTDIDS_DEFAULT "\0"\ "mtdparts=" MTDPARTS_DEFAULT "\0"\ - "dhcp_client_id=" MK_STR(MV_CI) "\0"\ - "dhcp_vendor-class-identifier=" MK_STR(MV_VCI) "\0"\ + "dhcp_client_id=" MV_CI "\0"\ + "dhcp_vendor-class-identifier=" MV_VCI "\0"\ "upd_uboot=dhcp;tftp bdi2000/u-boot-mergerbox-xp.bin;"\ "protect off all;erase $uboota +0xC0000;"\ "cp.b $loadaddr $uboota $filesize\0"\ @@ -602,17 +585,14 @@ "i2c_speed=i2c dev 0;i2c speed 300000;i2c dev 1;i2c speed 120000\0"\ "init_sdi_tx=i2c mw 21 6 0;i2c mw 21 2 0;i2c mw 21 3 0;sleep 1;"\ "i2c mw 21 2 ff;i2c mw 21 3 3c\0"\ - "splashimage=" MK_STR(MV_SPLAH_ADDR) "\0"\ + "splashimage=" __stringify(MV_SPLAH_ADDR) "\0"\ "" -#undef MK_STR -#undef XMK_STR - /* * FPGA */ #define CONFIG_FPGA_COUNT 1 -#define CONFIG_FPGA CONFIG_SYS_ALTERA_CYCLON2 +#define CONFIG_FPGA #define CONFIG_FPGA_ALTERA #define CONFIG_FPGA_CYCLON2