X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FM54418TWR.h;h=2866bfd85ff6279d6c8bd13bdb298c7088f7d4b8;hb=6463b73e0b25b058404c52b48c991abf4f8a94ce;hp=ba9ba0069868f452f19313185d6b3493bb5799d5;hpb=4bafceff0e9e5a36908031e41c69a6b37e82da58;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/M54418TWR.h b/include/configs/M54418TWR.h
index ba9ba00..2866bfd 100644
--- a/include/configs/M54418TWR.h
+++ b/include/configs/M54418TWR.h
@@ -1,10 +1,9 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Configuation settings for the Freescale MCF54418 TWR board.
  *
  * Copyright 2010-2012 Freescale Semiconductor, Inc.
  * TsiChung Liew (Tsi-Chung.Liew@freescale.com)
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
@@ -14,6 +13,8 @@
 #ifndef _M54418TWR_H
 #define _M54418TWR_H
 
+#include <linux/stringify.h>
+
 /*
  * High Level Configuration Options
  * (easy to change)
@@ -47,9 +48,7 @@
 #endif
 
 /* Network configuration */
-#define CONFIG_MCFFEC
 #ifdef CONFIG_MCFFEC
-#define CONFIG_MII			1
 #define CONFIG_MII_INIT		1
 #define CONFIG_SYS_DISCOVER_PHY
 #define CONFIG_SYS_RX_ETH_BUFFER	2
@@ -57,14 +56,6 @@
 #define CONFIG_SYS_TX_ETH_BUFFER	2
 #define CONFIG_HAS_ETH1
 
-#define CONFIG_SYS_FEC0_PINMUX		0
-#define CONFIG_SYS_FEC0_MIIBASE	CONFIG_SYS_FEC0_IOBASE
-#define CONFIG_SYS_FEC1_PINMUX		0
-#define CONFIG_SYS_FEC1_MIIBASE	CONFIG_SYS_FEC0_MIIBASE
-#define MCFFEC_TOUT_LOOP		50000
-#define CONFIG_SYS_FEC0_PHYADDR	0
-#define CONFIG_SYS_FEC1_PHYADDR	1
-
 #define CONFIG_ETHPRIME	"FEC0"
 #define CONFIG_IPADDR		192.168.1.2
 #define CONFIG_NETMASK		255.255.255.0
@@ -85,7 +76,7 @@
 #endif			/* CONFIG_SYS_DISCOVER_PHY */
 #endif
 
-#define CONFIG_HOSTNAME		M54418TWR
+#define CONFIG_HOSTNAME		"M54418TWR"
 
 #if defined(CONFIG_CF_SBF)
 /* ST Micro serial flash */
@@ -139,7 +130,6 @@
 
 /* Timer */
 #define CONFIG_MCFTMR
-#undef CONFIG_MCFPIT
 
 /* I2c */
 #undef CONFIG_SYS_FSL_I2C
@@ -153,20 +143,7 @@
 /* DSPI and Serial Flash */
 #define CONFIG_CF_DSPI
 #define CONFIG_SERIAL_FLASH
-#define CONFIG_HARD_SPI
 #define CONFIG_SYS_SBFHDR_SIZE		0x7
-#ifdef CONFIG_CMD_SPI
-
-#	define CONFIG_SYS_DSPI_CTAR0	(DSPI_CTAR_TRSZ(7) | \
-					 DSPI_CTAR_PCSSCK_1CLK | \
-					 DSPI_CTAR_PASC(0) | \
-					 DSPI_CTAR_PDT(0) | \
-					 DSPI_CTAR_CSSCK(0) | \
-					 DSPI_CTAR_ASC(0) | \
-					 DSPI_CTAR_DT(1))
-#	define CONFIG_SYS_DSPI_CTAR1	(CONFIG_SYS_DSPI_CTAR0)
-#	define CONFIG_SYS_DSPI_CTAR2	(CONFIG_SYS_DSPI_CTAR0)
-#endif
 
 /* Input, PCI, Flexbus, and VCO */
 #define CONFIG_EXTRA_CLOCK
@@ -203,8 +180,6 @@
 #define CONFIG_SYS_SDRAM_BASE		0x40000000
 #define CONFIG_SYS_SDRAM_SIZE		128	/* SDRAM size in MB */
 
-#define CONFIG_SYS_MEMTEST_START	(CONFIG_SYS_SDRAM_BASE + 0x400)
-#define CONFIG_SYS_MEMTEST_END		((CONFIG_SYS_SDRAM_SIZE - 3) << 20)
 #define CONFIG_SYS_DRAM_TEST
 
 #if defined(CONFIG_CF_SBF) || defined(CONFIG_SYS_NAND_BOOT)
@@ -235,31 +210,14 @@
 /* Configuration for environment
  * Environment is embedded in u-boot in the second sector of the flash
  */
-#if !defined(CONFIG_SERIAL_BOOT)  /*MRAM boot*/
-#define CONFIG_ENV_ADDR		(0x40000 - 0x1000) /*MRAM size 40000*/
-#define CONFIG_ENV_SIZE		0x1000
-#endif
 
-#if defined(CONFIG_CF_SBF)
-#define CONFIG_ENV_SPI_CS		1
-#define CONFIG_ENV_OFFSET		0x40000
-#define CONFIG_ENV_SIZE		0x2000
-#define CONFIG_ENV_SECT_SIZE		0x10000
-#endif
-#if defined(CONFIG_SYS_NAND_BOOT)
-#define CONFIG_ENV_OFFSET	0x80000
-#define CONFIG_ENV_SIZE	0x20000
-#define CONFIG_ENV_SECT_SIZE	0x20000
-#endif
 #undef CONFIG_ENV_OVERWRITE
 
 /* FLASH organization */
 #define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
 
-#undef CONFIG_SYS_FLASH_CFI
 #ifdef CONFIG_SYS_FLASH_CFI
 
-#define CONFIG_FLASH_CFI_DRIVER	1
 /* Max size that the board might have */
 #define CONFIG_SYS_FLASH_SIZE		0x1000000
 #define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
@@ -268,7 +226,6 @@
 /* max number of sectors on one chip */
 #define CONFIG_SYS_MAX_FLASH_SECT	270
 /* "Real" (hardware) sectors protection */
-#define CONFIG_SYS_FLASH_PROTECTION
 #define CONFIG_SYS_FLASH_CHECKSUM
 #define CONFIG_SYS_FLASH_BANKS_LIST	{ CONFIG_SYS_CS0_BASE }
 #else
@@ -285,14 +242,9 @@
 #ifdef CONFIG_CMD_JFFS2
 #define CONFIG_JFFS2_DEV		"nand0"
 #define CONFIG_JFFS2_PART_OFFSET	(0x800000)
-#define CONFIG_MTD_DEVICE
 
 #endif
 
-#ifdef CONFIG_CMD_UBI
-#define CONFIG_MTD_DEVICE	/* needed for mtdparts command */
-#define CONFIG_MTD_PARTITIONS	/* mtdparts and UBI support */
-#endif
 /* Cache Configuration */
 #define CONFIG_SYS_CACHELINE_SIZE	16
 #define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \