X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FM5253DEMO.h;h=75278f4dab71143c33519d2d4611d00e648328d2;hb=218e2c45af83f2cb7b1374b9023b4ced6eb0bb77;hp=0a416dc122662f213f7a52e7410a7623d66ffee1;hpb=167f699ba142193e67cade8d19127cfda723ce38;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h
index 0a416dc..75278f4 100644
--- a/include/configs/M5253DEMO.h
+++ b/include/configs/M5253DEMO.h
@@ -19,12 +19,6 @@
 	. = DEFINED(env_offset) ? env_offset : .; \
 	env/embedded.o(.text*);
 
-#ifdef CONFIG_IDE
-/* ATA */
-#	define CONFIG_IDE_PREINIT	1
-#	undef CONFIG_LBA48
-#endif
-
 #ifdef CONFIG_DRIVER_DM9000
 #	define CONFIG_DM9000_BASE	(CONFIG_SYS_CS1_BASE | 0x300)
 #	define DM9000_IO		CONFIG_DM9000_BASE
@@ -79,8 +73,6 @@
  */
 #define CONFIG_SYS_INIT_RAM_ADDR	0x20000000
 #define CONFIG_SYS_INIT_RAM_SIZE	0x10000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
 /*
  * Start addresses for the final memory configuration
@@ -98,12 +90,9 @@
  * the maximum mapped by the Linux kernel during initialization ??
  */
 #define CONFIG_SYS_BOOTMAPSZ		(CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20))
-#define CONFIG_SYS_BOOTM_LEN		(CONFIG_SYS_SDRAM_SIZE << 20)
 
 /* FLASH organization */
 #define CONFIG_SYS_FLASH_BASE		(CONFIG_SYS_CS0_BASE)
-#define CONFIG_SYS_MAX_FLASH_SECT	2048	/* max number of sectors on one chip */
-#define CONFIG_SYS_FLASH_ERASE_TOUT	1000
 
 #define FLASH_SST6401B		0x200
 #define SST_ID_xF6401B		0x236D236D
@@ -115,12 +104,9 @@
  * 0x30 is block erase in SST
  */
 #	define CONFIG_SYS_FLASH_SIZE		0x800000
-#	define CONFIG_SYS_FLASH_CFI_WIDTH	FLASH_CFI_16BIT
-#	define CONFIG_FLASH_CFI_LEGACY
 #else
 #	define CONFIG_SYS_SST_SECT		2048
 #	define CONFIG_SYS_SST_SECTSZ		0x1000
-#	define CONFIG_SYS_FLASH_WRITE_TOUT	500
 #endif
 
 /* Cache Configuration */
@@ -139,9 +125,6 @@
 #define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CEIB | \
 					 CF_CACR_DBWE)
 
-/* Port configuration */
-#define CONFIG_SYS_FECI2C		0xF0
-
 #define CONFIG_SYS_CS0_BASE		0xFF800000
 #define CONFIG_SYS_CS0_MASK		0x007F0021
 #define CONFIG_SYS_CS0_CTRL		0x00001D80