X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FM5235EVB.h;h=2a198e5cc3560653c14eadbeac037f98a43a9d8e;hb=a726075911c231e81ecbe12825840b6183bc10da;hp=e6c87efef0308968cb9db55d318d2ee49a3e0763;hpb=50bd0057ba8fceeb48533f8b1a652ccd0e170838;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index e6c87ef..2a198e5 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -4,23 +4,7 @@ * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. * TsiChung Liew (Tsi-Chung.Liew@freescale.com) * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -34,13 +18,10 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_MCF523x /* define processor family */ -#define CONFIG_M5235 /* define processor type */ #define CONFIG_MCFUART #define CONFIG_SYS_UART_PORT (0) #define CONFIG_BAUDRATE 115200 -#define CONFIG_SYS_BAUDRATE_TABLE { 9600 , 19200 , 38400 , 57600, 115200 } #undef CONFIG_WATCHDOG #define CONFIG_WATCHDOG_TIMEOUT 5000 /* timeout in milliseconds, max timeout is 6.71sec */ @@ -54,28 +35,17 @@ #define CONFIG_BOOTP_HOSTNAME /* Command line configuration */ -#include - -#define CONFIG_CMD_BOOTD #define CONFIG_CMD_CACHE #define CONFIG_CMD_DHCP -#define CONFIG_CMD_ELF -#define CONFIG_CMD_FLASH #define CONFIG_CMD_I2C -#define CONFIG_CMD_MEMORY -#define CONFIG_CMD_MISC #define CONFIG_CMD_MII -#define CONFIG_CMD_NET #define CONFIG_CMD_PCI #define CONFIG_CMD_PING #define CONFIG_CMD_REGINFO -#undef CONFIG_CMD_LOADB -#undef CONFIG_CMD_LOADS #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 # define CONFIG_MII_INIT 1 # define CONFIG_SYS_DISCOVER_PHY @@ -101,12 +71,11 @@ #undef CONFIG_MCFPIT /* I2C */ -#define CONFIG_FSL_I2C -#define CONFIG_HARD_I2C /* I2C with hw support */ -#undef CONFIG_SOFT_I2C /* I2C bit-banged */ -#define CONFIG_SYS_I2C_SPEED 80000 -#define CONFIG_SYS_I2C_SLAVE 0x7F -#define CONFIG_SYS_I2C_OFFSET 0x00000300 +#define CONFIG_SYS_I2C +#define CONFIG_SYS_i2C_FSL +#define CONFIG_SYS_FSL_I2C_SPEED 80000 +#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F +#define CONFIG_SYS_FSL_I2C_OFFSET 0x00000300 #define CONFIG_SYS_IMMR CONFIG_SYS_MBAR #define CONFIG_SYS_I2C_PINMUX_REG (gpio->par_qspi) #define CONFIG_SYS_I2C_PINMUX_CLR ~(GPIO_PAR_FECI2C_SCL_MASK | GPIO_PAR_FECI2C_SDA_MASK) @@ -116,12 +85,10 @@ #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ #define CONFIG_BOOTFILE "u-boot.bin" #ifdef CONFIG_MCFFEC -# define CONFIG_ETHADDR 00:e0:0c:bc:e5:60 # define CONFIG_IPADDR 192.162.1.2 # define CONFIG_NETMASK 255.255.255.0 # define CONFIG_SERVERIP 192.162.1.1 # define CONFIG_GATEWAYIP 192.162.1.1 -# define CONFIG_OVERWRITE_ETHADDR_ONCE #endif /* FEC_ENET */ #define CONFIG_HOSTNAME M5235EVB @@ -138,7 +105,6 @@ "" #define CONFIG_PRAM 512 /* 512 KB */ -#define CONFIG_SYS_PROMPT "-> " #define CONFIG_SYS_LONGHELP /* undef to save memory */ #if defined(CONFIG_KGDB) @@ -152,7 +118,6 @@ #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE+0x20000) -#define CONFIG_SYS_HZ 1000 #define CONFIG_SYS_CLK 75000000 #define CONFIG_SYS_CPU_CLK CONFIG_SYS_CLK * 2 @@ -167,10 +132,9 @@ * Definitions for initial stack pointer and data area (in DPRAM) */ #define CONFIG_SYS_INIT_RAM_ADDR 0x20000000 -#define CONFIG_SYS_INIT_RAM_END 0x10000 /* End of used area in internal SRAM */ +#define CONFIG_SYS_INIT_RAM_SIZE 0x10000 /* Size of used area in internal SRAM */ #define CONFIG_SYS_INIT_RAM_CTRL 0x21 -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE - 0x10) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE - 0x10) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- @@ -197,6 +161,7 @@ */ /* Initial Memory map for Linux */ #define CONFIG_SYS_BOOTMAPSZ (CONFIG_SYS_SDRAM_BASE + (CONFIG_SYS_SDRAM_SIZE << 20)) +#define CONFIG_SYS_BOOTM_LEN (CONFIG_SYS_SDRAM_SIZE << 20) /*----------------------------------------------------------------------- * FLASH organization @@ -215,13 +180,17 @@ # define CONFIG_SYS_FLASH_PROTECTION /* "Real" (hardware) sectors protection */ #endif -#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE << 16) +#define CONFIG_SYS_FLASH_BASE (CONFIG_SYS_CS0_BASE) /* Configuration for environment * Environment is embedded in u-boot in the second sector of the flash */ #define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_IS_EMBEDDED 1 + +#define LDS_BOARD_TEXT \ + . = DEFINED(env_offset) ? env_offset : .; \ + common/env_embedded.o (.text); + #ifdef NORFLASH_PS32BIT # define CONFIG_ENV_OFFSET (0x8000) # define CONFIG_ENV_SIZE 0x4000 @@ -237,6 +206,18 @@ */ #define CONFIG_SYS_CACHELINE_SIZE 16 +#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 8) +#define DCACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ + CONFIG_SYS_INIT_RAM_SIZE - 4) +#define CONFIG_SYS_ICACHE_INV (CF_CACR_CINV) +#define CONFIG_SYS_CACHE_ACR0 (CONFIG_SYS_SDRAM_BASE | \ + CF_ADDRMASK(CONFIG_SYS_SDRAM_SIZE) | \ + CF_ACR_EN | CF_ACR_SM_ALL) +#define CONFIG_SYS_CACHE_ICACR (CF_CACR_CENB | CF_CACR_DISD | \ + CF_CACR_CEIB | CF_CACR_DCM | \ + CF_CACR_EUSP) + /*----------------------------------------------------------------------- * Chipselect bank definitions */ @@ -251,13 +232,13 @@ * CS7 - Available */ #ifdef NORFLASH_PS32BIT -# define CONFIG_SYS_CS0_BASE 0xFFC0 +# define CONFIG_SYS_CS0_BASE 0xFFC00000 # define CONFIG_SYS_CS0_MASK 0x003f0001 -# define CONFIG_SYS_CS0_CTRL 0x1D00 +# define CONFIG_SYS_CS0_CTRL 0x00001D00 #else -# define CONFIG_SYS_CS0_BASE 0xFFE0 +# define CONFIG_SYS_CS0_BASE 0xFFE00000 # define CONFIG_SYS_CS0_MASK 0x001f0001 -# define CONFIG_SYS_CS0_CTRL 0x1D80 +# define CONFIG_SYS_CS0_CTRL 0x00001D80 #endif #endif /* _M5329EVB_H */