X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FM5208EVBE.h;h=e14650fe0d40467832ade3e249cde62ad94ed5ba;hb=54f80dd2908af0b851816cf062edf2d454948397;hp=6dfa3dd0f02af7bc51ff8bc85646df84782a6be5;hpb=aa6e94deabb45154cea07ad44c4a5c047bca078b;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h
index 6dfa3dd..e14650f 100644
--- a/include/configs/M5208EVBE.h
+++ b/include/configs/M5208EVBE.h
@@ -13,20 +13,10 @@
  * High Level Configuration Options
  * (easy to change)
  */
-#define CONFIG_SYS_UART_PORT		(0)
-
-#define CONFIG_WATCHDOG_TIMEOUT		5000
+#define CFG_SYS_UART_PORT		(0)
 
 /* I2C */
 
-#ifdef CONFIG_MCFFEC
-#	define CONFIG_IPADDR	192.162.1.2
-#	define CONFIG_NETMASK	255.255.255.0
-#	define CONFIG_SERVERIP	192.162.1.1
-#	define CONFIG_GATEWAYIP	192.162.1.1
-#endif				/* CONFIG_MCFFEC */
-
-#define CONFIG_HOSTNAME		"M5208EVBe"
 #define CONFIG_EXTRA_ENV_SETTINGS		\
 	"netdev=eth0\0"				\
 	"loadaddr=40010000\0"			\
@@ -41,11 +31,11 @@
 
 #define CONFIG_PRAM		512	/* 512 KB */
 
-#define CONFIG_SYS_CLK		166666666	/* CPU Core Clock */
-#define CONFIG_SYS_PLL_ODR	0x36
-#define CONFIG_SYS_PLL_FDR	0x7D
+#define CFG_SYS_CLK		166666666	/* CPU Core Clock */
+#define CFG_SYS_PLL_ODR	0x36
+#define CFG_SYS_PLL_FDR	0x7D
 
-#define CONFIG_SYS_MBAR		0xFC000000
+#define CFG_SYS_MBAR		0xFC000000
 
 /*
  * Low Level Configuration Settings
@@ -53,9 +43,9 @@
  * You should know what you are doing if you make changes here.
  */
 /* Definitions for initial stack pointer and data area (in DPRAM) */
-#define CONFIG_SYS_INIT_RAM_ADDR	0x80000000
-#define CONFIG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
-#define CONFIG_SYS_INIT_RAM_CTRL	0x221
+#define CFG_SYS_INIT_RAM_ADDR	0x80000000
+#define CFG_SYS_INIT_RAM_SIZE		0x4000	/* Size of used area in internal SRAM */
+#define CFG_SYS_INIT_RAM_CTRL	0x221
 
 /*
  * Start addresses for the final memory configuration
@@ -75,14 +65,14 @@
  * have to be in the first 8 MB of memory, since this is
  * the maximum mapped by the Linux kernel during initialization ??
  */
-#define CONFIG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
+#define CFG_SYS_BOOTMAPSZ		(CFG_SYS_SDRAM_BASE + (CFG_SYS_SDRAM_SIZE << 20))
 
 /* FLASH organization */
 #ifdef CONFIG_SYS_FLASH_CFI
-#	define CONFIG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
+#	define CFG_SYS_FLASH_SIZE		0x800000	/* Max size that the board might have */
 #endif
 
-#define CONFIG_SYS_FLASH_BASE		CONFIG_SYS_CS0_BASE
+#define CFG_SYS_FLASH_BASE		CFG_SYS_CS0_BASE
 
 /*
  * Configuration for environment
@@ -95,15 +85,15 @@
 
 /* Cache Configuration */
 
-#define ICACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 8)
-#define DCACHE_STATUS			(CONFIG_SYS_INIT_RAM_ADDR + \
-					 CONFIG_SYS_INIT_RAM_SIZE - 4)
-#define CONFIG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
-#define CONFIG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
+#define ICACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 8)
+#define DCACHE_STATUS			(CFG_SYS_INIT_RAM_ADDR + \
+					 CFG_SYS_INIT_RAM_SIZE - 4)
+#define CFG_SYS_ICACHE_INV		(CF_CACR_CINV | CF_CACR_INVI)
+#define CFG_SYS_CACHE_ACR0		(CFG_SYS_SDRAM_BASE | \
 					 CF_ADDRMASK(CFG_SYS_SDRAM_SIZE) | \
 					 CF_ACR_EN | CF_ACR_SM_ALL)
-#define CONFIG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
+#define CFG_SYS_CACHE_ICACR		(CF_CACR_CENB | CF_CACR_CINV | \
 					 CF_CACR_DISD | CF_CACR_INVI | \
 					 CF_CACR_CEIB | CF_CACR_DCM | \
 					 CF_CACR_EUSP)
@@ -117,8 +107,8 @@
  * CS4 - Available
  * CS5 - Available
  */
-#define CONFIG_SYS_CS0_BASE		0
-#define CONFIG_SYS_CS0_MASK		0x007F0001
-#define CONFIG_SYS_CS0_CTRL		0x00001FA0
+#define CFG_SYS_CS0_BASE		0
+#define CFG_SYS_CS0_MASK		0x007F0001
+#define CFG_SYS_CS0_CTRL		0x00001FA0
 
 #endif				/* _M5208EVBE_H */