X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FJSE.h;h=8aac447c1a82c10b23aa3df1398d000cc8bea5a2;hb=0defddc851edfc34bcf3c3379fe74b11dc01a493;hp=80c70e48869d6b2d617d2efe813397beb727ff8d;hpb=18cc7afd9a153a66854af862d14ba01c5496cf07;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/JSE.h b/include/configs/JSE.h
index 80c70e4..8aac447 100644
--- a/include/configs/JSE.h
+++ b/include/configs/JSE.h
@@ -2,23 +2,7 @@
  * (C) Copyright 2003 Picture Elements, Inc.
  * Stephen Williams <steve@icarus.com>
  *
- * See file CREDITS for list of people who contributed to this
- * project.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; either version 2 of
- * the License, or (at your option) any later version.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
- * GNU General Public License for more details.
- *
- * You should have received a copy of the GNU General Public License
- * along with this program; if not, write to the Free Software
- * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
- * MA 02111-1307 USA
+ * SPDX-License-Identifier:	GPL-2.0+
  */
 
 /*
@@ -37,7 +21,7 @@
   /* JSE has a PPC405GPr */
 #define CONFIG_405GP 1
   /* ... which is a 4xxx series */
-#define CONFIG_4xx   1
+#define CONFIG_4x   1
   /* ... with a 33MHz OSC. connected to the SysCLK input */
 #define CONFIG_SYS_CLK_FREQ	33333333
   /* ... with on-chip memory here (4KBytes) */
@@ -46,6 +30,8 @@
   /* Do not set up locked dcache as init ram. */
 #undef CONFIG_SYS_INIT_DCACHE_CS
 
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
   /* Map the SystemACE chip (CS#1) here. (Must be a multiple of 1Meg) */
 #define CONFIG_SYSTEMACE 1
 #define CONFIG_SYS_SYSTEMACE_BASE 0xf0000000
@@ -57,10 +43,9 @@
   /* ... place INIT RAM in the OCM address */
 # define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR
   /* ... give it the whole init ram */
-# define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE
+# define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE
   /* ... Shave a bit off the end for global data */
-# define CONFIG_SYS_GBL_DATA_SIZE	128
-# define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+# define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
   /* ... and place the stack pointer at the top of what's left. */
 # define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET
 
@@ -95,18 +80,16 @@
 #define CONFIG_ENV_OFFSET	0x00
 #define CONFIG_ENV_SIZE	512
 
-
   /* The JSE connects UART1 to the console tap connector. */
-#define CONFIG_UART1_CONSOLE	1
+#define CONFIG_CONS_INDEX	2
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
   /* Set console baudrate to 9600 */
 #define CONFIG_BAUDRATE		9600
 
-/* Size (bytes) of interrupt driven serial port buffer.
- * Set to 0 to use polling instead of interrupts.
- * Setting to 0 will also disable RTS/CTS handshaking.
- */
-#undef CONFIG_SERIAL_SOFTWARE_FIFO
-
 /*
  * Configuration related to auto-boot.
  *
@@ -135,7 +118,6 @@
 #define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		1	/* PHY address			*/
-#define CONFIG_NET_MULTI
 
 
 /*
@@ -174,12 +156,8 @@
  * Miscellaneous configurable options
  */
 #define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
-#define CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/
 
 #define CONFIG_SYS_HUSH_PARSER			/* use "hush" command parser	*/
-#ifdef	CONFIG_SYS_HUSH_PARSER
-#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
-#endif
 
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
@@ -215,10 +193,11 @@
 
 #define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */
 
-#define CONFIG_HARD_I2C		1	/* I2C with hardware support	*/
-#undef	CONFIG_SOFT_I2C			/* I2C bit-banged		*/
-#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
-#define CONFIG_SYS_I2C_SLAVE		0x7F
+#define CONFIG_SYS_I2C
+#define CONFIG_SYS_I2C_PPC4XX
+#define CONFIG_SYS_I2C_PPC4XX_CH0
+#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000
+#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0		0x7F
 
 
 /*-----------------------------------------------------------------------
@@ -230,6 +209,7 @@
 #define PCI_HOST_AUTO	2		/* detected via arbiter enable	*/
 
 #define CONFIG_PCI			/* include pci support		*/
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function	*/
 #undef	CONFIG_PCI_PNP			/* do pci plug-and-play		*/
 					/* resource configuration	*/
@@ -294,15 +274,6 @@
 /* Configuration Port location */
 #define CONFIG_PORT_ADDR	0xF0000500
 
-
-/*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
-#define BOOTFLAG_WARM	0x02		/* Software reboot			*/
-
 #if defined(CONFIG_CMD_KGDB)
 #define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
 #define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */