X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FHH405.h;h=7ff03b17a70f082f30f7d63be3af058354891997;hb=0e8d158664a913392cb01fb11a948d83f72e105e;hp=ea8e61a764bf25d25e60de0fc160aac6d75a9d8d;hpb=81735b2568cf634d601c0d4a1bbc3a3882bc8eda;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/HH405.h b/include/configs/HH405.h
index ea8e61a..7ff03b1 100644
--- a/include/configs/HH405.h
+++ b/include/configs/HH405.h
@@ -41,7 +41,7 @@
 
 #define CONFIG_405EP		1	/* This is a PPC405 CPU		*/
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
-#define CONFIG_HH405		1	/* ...on a HH405 board 	        */
+#define CONFIG_HH405		1	/* ...on a HH405 board	        */
 
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
@@ -217,7 +217,8 @@
 #define CFG_NAND_CLE            (0x80000000 >> 2)   /* our CLE is GPIO2 */
 #define CFG_NAND_ALE            (0x80000000 >> 3)   /* our ALE is GPIO3 */
 
-#define CFG_NAND_SKIP_BAD_DOT_I      1  /* ".i" read skips bad blocks   */
+#define CFG_NAND_SKIP_BAD_DOT_I 1       /* ".i" read skips bad blocks   */
+#define CFG_NAND_QUIET          1
 
 /*-----------------------------------------------------------------------
  * PCI stuff
@@ -319,9 +320,9 @@
 /*-----------------------------------------------------------------------
  * Environment Variable setup
  */
-#define CFG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
-#define CFG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
-#define CFG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
+#define CONFIG_ENV_IS_IN_EEPROM    1       /* use EEPROM for environment vars */
+#define CONFIG_ENV_OFFSET          0x100   /* environment starts at the beginning of the EEPROM */
+#define CONFIG_ENV_SIZE            0x700   /* 2048 bytes may be used for env vars*/
 				   /* total size of a CAT24WC16 is 2048 bytes */
 
 #define CFG_NVRAM_BASE_ADDR	0xF4080000		/* NVRAM base address	*/
@@ -362,16 +363,6 @@
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
 /*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's    */
-					/* have only 8kB, 16kB is save here     */
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
-/*-----------------------------------------------------------------------
  * External Bus Controller (EBC) Setup
  */
 
@@ -416,7 +407,7 @@
 /*
  * define UIC_EXT0 ... UIC_EXT6 if external interrupt is active high
  */
-#define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_EXT6)
+#define CFG_UIC0_POLARITY       (0xFFFFFF80 | UIC_MASK(VECNUM_EIRQ6))
 
 /*-----------------------------------------------------------------------
  * FPGA stuff