X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FCPU87.h;h=db423a0ba9477ac7faa863d81c3f45117518f353;hb=bb1f8b4f8bb0bfce52e0faa4637b975b745824b3;hp=9a98e5c191e183b5323731a4f9761d9eb12773e4;hpb=7b230f61db319d87d51449d4620d520822813fbb;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/CPU87.h b/include/configs/CPU87.h
index 9a98e5c..db423a0 100644
--- a/include/configs/CPU87.h
+++ b/include/configs/CPU87.h
@@ -69,9 +69,7 @@
  * for FCC)
  *
  * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be
- * defined elsewhere (as for the console), or CFG_CMD_NET must be removed
- * from CONFIG_COMMANDS to remove support for networking.
- *
+ * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset.
  */
 #undef	CONFIG_ETHER_ON_SCC		/* define if ether on SCC	*/
 #define CONFIG_ETHER_ON_FCC		/* define if ether on FCC	*/
@@ -116,7 +114,7 @@
 
 #define CONFIG_PREBOOT								\
 	"echo; "								\
-	"echo Type \"run flash_nfs\" to mount root filesystem over NFS; "	\
+	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS; "	\
 	"echo"
 
 #undef	CONFIG_BOOTARGS
@@ -167,36 +165,40 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #undef	CFG_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/
 
-#define CONFIG_BOOTP_MASK	(CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE)
+/*
+ * BOOTP options
+ */
+#define CONFIG_BOOTP_SUBNETMASK
+#define CONFIG_BOOTP_GATEWAY
+#define CONFIG_BOOTP_HOSTNAME
+#define CONFIG_BOOTP_BOOTPATH
+#define CONFIG_BOOTP_BOOTFILESIZE
+
+
+/*
+ * Command line configuration.
+ */
+#include <config_cmd_default.h>
+
+#define CONFIG_CMD_BEDBUG
+#define CONFIG_CMD_DATE
+#define CONFIG_CMD_DOC
+#define CONFIG_CMD_EEPROM
+#define CONFIG_CMD_I2C
 
 #ifdef CONFIG_PCI
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_BEDBUG | \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_DOC	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_I2C	| \
-				 CFG_CMD_PCI)
-#else	/* ! PCI */
-#define CONFIG_COMMANDS		(CONFIG_CMD_DFL | \
-				 CFG_CMD_BEDBUG | \
-				 CFG_CMD_DATE	| \
-				 CFG_CMD_DOC	| \
-				 CFG_CMD_EEPROM | \
-				 CFG_CMD_I2C	)
-#endif	/* CONFIG_PCI */
-
-/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */
-#include <cmd_confdefs.h>
-
-#define CFG_NAND_LEGACY
+    #define CONFIG_CMD_PCI
+#endif
+
+
+#define CONFIG_NAND_LEGACY
 
 /*
  * Miscellaneous configurable options
  */
 #define CFG_LONGHELP			/* undef to save memory		*/
 #define CFG_PROMPT	"=> "		/* Monitor Command Prompt	*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 #define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
 #else
 #define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
@@ -345,7 +347,7 @@
 #endif
 #else
 /* environment is in EEPROM */
-#define CFG_ENV_IS_IN_EEPROM	1
+#define CONFIG_ENV_IS_IN_EEPROM	1
 #define CFG_I2C_EEPROM_ADDR	0x58	/* EEPROM X24C16		*/
 #define CFG_I2C_EEPROM_ADDR_LEN 1
 /* mask of address bits that overflow into the "EEPROM chip address"	*/
@@ -369,7 +371,7 @@
  * Cache Configuration
  */
 #define CFG_CACHELINE_SIZE	32	/* For MPC8260 CPU		*/
-#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
+#if defined(CONFIG_CMD_KGDB)
 # define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
 #endif
 
@@ -455,7 +457,7 @@
 #define CFG_MIN_AM_MASK 0xC0000000
 
 /*
- * we use the same values for 32 MB and 128 MB SDRAM
+ * we use the same values for 32 MB, 128 MB and 256 MB SDRAM
  * refresh rate = 7.68 uS (100 MHz Bus Clock)
  */
 
@@ -510,6 +512,24 @@
 			 PSDMR_WRC_1C			|\
 			 PSDMR_CL_2)
 
+	/* SDRAM initialization values for 10-column chips
+	 */
+#define CFG_OR2_10COL	(CFG_MIN_AM_MASK		|\
+			 ORxS_BPD_4			|\
+			 ORxS_ROWST_PBI1_A4		|\
+			 ORxS_NUMR_13)
+
+#define CFG_PSDMR_10COL	(PSDMR_PBI			|\
+			 PSDMR_SDAM_A17_IS_A5		|\
+			 PSDMR_BSMA_A13_A15		|\
+			 PSDMR_SDA10_PBI1_A6		|\
+			 PSDMR_RFRC_7_CLK		|\
+			 PSDMR_PRETOACT_2W		|\
+			 PSDMR_ACTTORW_2W		|\
+			 PSDMR_LDOTOPRE_1C		|\
+			 PSDMR_WRC_1C			|\
+			 PSDMR_CL_2)
+
 /*
  * Init Memory Controller:
  *
@@ -588,9 +608,9 @@
 			 BRx_MS_SDRAM_P			|\
 			 BRx_V)
 
-#define CFG_OR2_PRELIM	 CFG_OR2_9COL
+#define CFG_OR2_PRELIM	 CFG_OR2_8COL
 
-#define CFG_PSDMR	 CFG_PSDMR_9COL
+#define CFG_PSDMR	 CFG_PSDMR_8COL
 #endif /* CFG_RAMBOOT */
 
 /* Bank 3 - Dual Ported SRAM