X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FCPU86.h;h=c589f288789d3dbd37e9da0ac0723a16a8fa1caf;hb=b706d63559aeec352bc72dd86d7d5423c15f6a60;hp=9712d479c17b4a10c18eae6e6877793763c500a3;hpb=3bac351370ef7cbf9d2af27ba52bee1703ad677e;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/CPU86.h b/include/configs/CPU86.h index 9712d47..c589f28 100644 --- a/include/configs/CPU86.h +++ b/include/configs/CPU86.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2001 + * (C) Copyright 2001-2005 * Wolfgang Denk, DENX Software Engineering, wd@denx.de. * * See file CREDITS for list of people who contributed to this @@ -35,6 +35,7 @@ #define CONFIG_MPC8260 1 /* This is an MPC8260 CPU */ #define CONFIG_CPU86 1 /* ...on a CPU86 board */ +#define CONFIG_CPM2 1 /* Has a CPM2 */ /* * select serial console configuration @@ -67,9 +68,7 @@ * for FCC) * * if CONFIG_ETHER_NONE is defined, then either the ethernet routines must be - * defined elsewhere (as for the console), or CFG_CMD_NET must be removed - * from CONFIG_COMMANDS to remove support for networking. - * + * defined elsewhere (as for the console), or CONFIG_CMD_NET must be unset. */ #undef CONFIG_ETHER_ON_SCC /* define if ether on SCC */ #define CONFIG_ETHER_ON_FCC /* define if ether on FCC */ @@ -109,8 +108,6 @@ #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ -#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ - #define CONFIG_PREBOOT \ "echo; " \ "echo Type \"run flash_nfs\" to mount root filesystem over NFS; " \ @@ -119,8 +116,8 @@ #undef CONFIG_BOOTARGS #define CONFIG_BOOTCOMMAND \ "bootp; " \ - "setenv bootargs root=/dev/nfs rw nfsroot=$(serverip):$(rootpath) " \ - "ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask):$(hostname)::off; " \ + "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ "bootm" /*----------------------------------------------------------------------- @@ -164,24 +161,37 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT|CONFIG_BOOTP_BOOTFILESIZE) +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + + +/* + * Command line configuration. + */ +#include -#define CONFIG_COMMANDS (CONFIG_CMD_DFL | \ - CFG_CMD_BEDBUG | \ - CFG_CMD_EEPROM | \ - CFG_CMD_DATE | \ - CFG_CMD_I2C | \ - CFG_CMD_DOC ) +#define CONFIG_CMD_BEDBUG +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DOC +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_NFS +#define CONFIG_CMD_SNTP -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include /* * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -346,7 +356,7 @@ * Cache Configuration */ #define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPU */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ #endif @@ -361,7 +371,7 @@ * HID1 has only read-only information - nothing to set. */ #define CFG_HID0_INIT (HID0_ICE|HID0_DCE|HID0_ICFI|\ - HID0_DCI|HID0_IFEM|HID0_ABE) + HID0_DCI|HID0_IFEM|HID0_ABE) #define CFG_HID0_FINAL (HID0_IFEM|HID0_ABE) #define CFG_HID2 0 @@ -394,10 +404,10 @@ */ #if defined(CONFIG_WATCHDOG) #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) + SYPCR_SWRI|SYPCR_SWP|SYPCR_SWE) #else #define CFG_SYPCR (SYPCR_SWTC|SYPCR_BMT|SYPCR_PBME|SYPCR_LBME|\ - SYPCR_SWRI|SYPCR_SWP) + SYPCR_SWRI|SYPCR_SWP) #endif /* CONFIG_WATCHDOG */ /*----------------------------------------------------------------------- @@ -498,55 +508,55 @@ /* Bank 0 - Boot ROM */ #define CFG_BR0_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 1 - FLASH */ #define CFG_BR1_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) #else /* CONFIG_BOOT_ROM */ /* Bank 0 - FLASH */ #define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR0_PRELIM (P2SZ_TO_AM(CFG_FLASH_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 1 - Boot ROM */ #define CFG_BR1_PRELIM ((CFG_BOOTROM_BASE & BRx_BA_MSK)|\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR1_PRELIM (P2SZ_TO_AM(CFG_BOOTROM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_3_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_3_CLK |\ + ORxU_EHTR_8IDLE) #endif /* CONFIG_BOOT_ROM */ @@ -555,9 +565,9 @@ */ #ifndef CFG_RAMBOOT #define CFG_BR2_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_64 |\ - BRx_MS_SDRAM_P |\ - BRx_V) + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) #define CFG_OR2_PRELIM CFG_OR2_9COL @@ -567,88 +577,88 @@ /* Bank 3 - Dual Ported SRAM */ #define CFG_BR3_PRELIM ((CFG_DPSRAM_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_DPSRAM_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) /* Bank 4 - DiskOnChip */ #define CFG_BR4_PRELIM ((CFG_DOC_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR4_PRELIM (P2SZ_TO_AM(CFG_DOC_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_5_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_ACS_DIV2 |\ + ORxG_SCY_5_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 5 - FDC37C78 controller */ #define CFG_BR5_PRELIM ((CFG_FDC37C78_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR5_PRELIM (P2SZ_TO_AM(CFG_FDC37C78_SIZE) |\ - ORxG_ACS_DIV2 |\ - ORxG_SCY_8_CLK |\ - ORxU_EHTR_8IDLE) + ORxG_ACS_DIV2 |\ + ORxG_SCY_8_CLK |\ + ORxU_EHTR_8IDLE) /* Bank 6 - Board control registers */ #define CFG_BR6_PRELIM ((CFG_BCRS_BASE & BRx_BA_MSK) |\ - BRx_PS_8 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_8 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR6_PRELIM (P2SZ_TO_AM(CFG_BCRS_SIZE) |\ - ORxG_CSNT |\ - ORxG_SCY_5_CLK) + ORxG_CSNT |\ + ORxG_SCY_5_CLK) /* Bank 7 - VME Extended Access Range */ #define CFG_BR7_PRELIM ((CFG_VMEEAR_BASE & BRx_BA_MSK) |\ - BRx_PS_32 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR7_PRELIM (P2SZ_TO_AM(CFG_VMEEAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) /* Bank 8 - VME Standard Access Range */ #define CFG_BR8_PRELIM ((CFG_VMESAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR8_PRELIM (P2SZ_TO_AM(CFG_VMESAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) /* Bank 9 - VME Short I/O Access Range */ #define CFG_BR9_PRELIM ((CFG_VMESIOAR_BASE & BRx_BA_MSK) |\ - BRx_PS_16 |\ - BRx_MS_GPCM_P |\ - BRx_V) + BRx_PS_16 |\ + BRx_MS_GPCM_P |\ + BRx_V) #define CFG_OR9_PRELIM (P2SZ_TO_AM(CFG_VMESIOAR_SIZE) |\ - ORxG_CSNT |\ - ORxG_ACS_DIV1 |\ - ORxG_SCY_5_CLK |\ - ORxG_SETA) + ORxG_CSNT |\ + ORxG_ACS_DIV1 |\ + ORxG_SCY_5_CLK |\ + ORxG_SETA) #endif /* __CONFIG_H */