X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FCPCI405DT.h;h=a8029eae9d18fb43d7f0f6f54f204cac85e3ce74;hb=f33fca22e76f20e4e4793810ca7a06a4805a6cf4;hp=e2652e6aa6e130473399f8b16ca6958cb2ac0059;hpb=f2c2a937d8c4a44f63ff88bf82023e03a29497a2;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/CPCI405DT.h b/include/configs/CPCI405DT.h
index e2652e6..a8029ea 100644
--- a/include/configs/CPCI405DT.h
+++ b/include/configs/CPCI405DT.h
@@ -111,8 +111,6 @@
 
 #undef  CONFIG_AUTO_UPDATE              /* autoupdate via compactflash  */
 
-#define CFG_NAND_LEGACY
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
@@ -321,16 +319,6 @@
 #define CFG_EEPROM_PAGE_WRITE_DELAY_MS	10   /* and takes up to 10 msec */
 #define CFG_EEPROM_PAGE_WRITE_ENABLE
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
 /*
  * Init Memory Controller:
  *