X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FCPCI405AB.h;h=1e9597dc619420bb4fb92ae8930c77f6e34cf864;hb=bb701283a8dcb2521000fe437f19a83cadc98b02;hp=1aefbbac686e3f4b7d5441ac0284902993525229;hpb=3b3bff4cbf2cb14f9a3e7d03f26ebab900efe4ae;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/CPCI405AB.h b/include/configs/CPCI405AB.h
index 1aefbba..1e9597d 100644
--- a/include/configs/CPCI405AB.h
+++ b/include/configs/CPCI405AB.h
@@ -100,9 +100,6 @@
 
 #define CONFIG_SUPPORT_VFAT
 
-#define CFG_NAND_LEGACY
-
-
 #undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
 
 #define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0	*/
@@ -291,16 +288,6 @@
 #define CFG_NVRAM_SIZE		(32*1024)		/* NVRAM size		*/
 #define CFG_VXWORKS_MAC_PTR     (CFG_NVRAM_BASE_ADDR+0x6900) /* VxWorks eth-addr*/
 
-/*-----------------------------------------------------------------------
- * Cache Configuration
- */
-#define CFG_DCACHE_SIZE		16384	/* For AMCC 405 CPUs, older 405 ppc's	*/
-					/* have only 8kB, 16kB is save here	*/
-#define CFG_CACHELINE_SIZE	32	/* ...			*/
-#if defined(CONFIG_CMD_KGDB)
-#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value	*/
-#endif
-
 /*
  * Init Memory Controller:
  *