X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FCPCI4052.h;h=ef8abf6466c336c806fb8de663215863b45c9234;hb=bb1f8b4f8bb0bfce52e0faa4637b975b745824b3;hp=d1498eed3c4bc6619b5d0be030d233fda3386a8e;hpb=700a0c648df72f2c8e0589c0d0470b5ffd7cab7b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/CPCI4052.h b/include/configs/CPCI4052.h index d1498ee..ef8abf6 100644 --- a/include/configs/CPCI4052.h +++ b/include/configs/CPCI4052.h @@ -37,6 +37,7 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_CPCI405 1 /* ...on a CPCI405 board */ #define CONFIG_CPCI405_VER2 1 /* ...version 2 */ +#undef CONFIG_CPCI405_6U /* enable this for 6U boards */ #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ @@ -56,50 +57,48 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_LXT971_NO_SLEEP 1 /* disable sleep mode in LXT971 */ +#define CONFIG_RESET_PHY_R 1 /* use reset_phy() to disable phy sleep mode */ + +#define CONFIG_NET_MULTI 1 +#undef CONFIG_HAS_ETH1 #define CONFIG_RTC_M48T35A 1 /* ST Electronics M48 timekeeper */ -#define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | \ - CONFIG_BOOTP_DNS | \ - CONFIG_BOOTP_DNS2 | \ - CONFIG_BOOTP_SEND_HOSTNAME ) - -#define CONFIG_COMMANDS ( CONFIG_CMD_DFL | \ - CFG_CMD_DHCP | \ - CFG_CMD_PCI | \ - CFG_CMD_IRQ | \ - CFG_CMD_IDE | \ - CFG_CMD_FAT | \ - CFG_CMD_ELF | \ - CFG_CMD_DATE | \ - CFG_CMD_JFFS2 | \ - CFG_CMD_I2C | \ - CFG_CMD_MII | \ - CFG_CMD_PING | \ - CFG_CMD_BSP | \ - CFG_CMD_EEPROM ) - -#if 0 /* test-only */ -#define CONFIG_NETCONSOLE -#define CONFIG_NET_MULTI - -#ifdef CONFIG_NET_MULTI -#define CONFIG_PHY1_ADDR 1 /* PHY address: for NetConsole */ -#endif -#endif +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME + + +/* + * Command line configuration. + */ +#include + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_PCI +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_IDE +#define CONFIG_CMD_FAT +#define CONFIG_CMD_ELF +#define CONFIG_CMD_DATE +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_BSP +#define CONFIG_CMD_EEPROM #define CONFIG_MAC_PARTITION #define CONFIG_DOS_PARTITION #define CONFIG_SUPPORT_VFAT -#if 0 /* test-only */ -#define CONFIG_AUTO_UPDATE 1 /* autoupdate via compactflash */ -#endif - -/* this must be included AFTER the definition of CONFIG_COMMANDS (if any) */ -#include - #undef CONFIG_WATCHDOG /* watchdog disabled */ #define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */ @@ -115,7 +114,7 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#if defined(CONFIG_CMD_KGDB) #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ @@ -147,6 +146,8 @@ #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ +#define CONFIG_CMDLINE_EDITING /* add command line history */ + #define CONFIG_LOOPW 1 /* enable loopw command */ #define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ @@ -178,8 +179,8 @@ #define CFG_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ #define CFG_PCI_SUBSYS_DEVICEID2 0x0406 /* PCI Device ID: CPCI-405-A */ #define CFG_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CFG_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CFG_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ +#define CFG_PCI_PTM1LA (bd->bi_memstart) /* point to sdram */ +#define CFG_PCI_PTM1MS (~(bd->bi_memsize - 1) | 1) /* memsize, enable hard-wired to 1 */ #define CFG_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ #define CFG_PCI_PTM2LA 0xffc00000 /* point to flash */ #define CFG_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ @@ -220,6 +221,10 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP + /*----------------------------------------------------------------------- * FLASH organization */ @@ -242,29 +247,6 @@ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ - -/* - * JFFS2 partitions - */ - -/* No command line, one static partition, use whole device */ -#undef CONFIG_JFFS2_CMDLINE -#define CONFIG_JFFS2_DEV "nor0" -#define CONFIG_JFFS2_PART_SIZE 0xFFFFFFFF -#define CONFIG_JFFS2_PART_OFFSET 0x00000000 - -/* mtdparts command line support */ - -/* Use first bank for JFFS2, second bank contains U-Boot. - * - * Note: fake mtd_id's used, no linux mtd map file. - */ -/* -#define CONFIG_JFFS2_CMDLINE -#define MTDIDS_DEFAULT "nor0=cpci4052-0" -#define MTDPARTS_DEFAULT "mtdparts=cpci4052-0:-(jffs2)" -*/ - #if 0 /* Use NVRAM for environment variables */ /*----------------------------------------------------------------------- * NVRAM organization @@ -276,7 +258,7 @@ #else /* Use EEPROM for environment variables */ -#define CFG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ #define CFG_ENV_OFFSET 0x000 /* environment starts at the beginning of the EEPROM */ #define CFG_ENV_SIZE 0x800 /* 2048 bytes may be used for env vars*/ /* total size of a CAT24WC16 is 2048 bytes */ @@ -303,16 +285,6 @@ #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ #define CFG_EEPROM_PAGE_WRITE_ENABLE -/*----------------------------------------------------------------------- - * Cache Configuration - */ -#define CFG_DCACHE_SIZE 16384 /* For IBM 405 CPUs, older 405 ppc's */ - /* have only 8kB, 16kB is save here */ -#define CFG_CACHELINE_SIZE 32 /* ... */ -#if (CONFIG_COMMANDS & CFG_CMD_KGDB) -#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ -#endif - /* * Init Memory Controller: *