X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FCMS700.h;h=bd5d4e904b4f7f8de393a2e5bafd3e05316f9bf7;hb=3765b3e7bd0f8e46914d417f29cbcb0c72b1acf7;hp=d58f50848464cee465a7ff82906aec3cff79bb5f;hpb=50bd0057ba8fceeb48533f8b1a652ccd0e170838;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/CMS700.h b/include/configs/CMS700.h index d58f508..bd5d4e9 100644 --- a/include/configs/CMS700.h +++ b/include/configs/CMS700.h @@ -2,23 +2,7 @@ * (C) Copyright 2005 * Matthias Fuchs, esd gmbh germany, matthias.fuchs@esd-electronics.com * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA + * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -37,6 +21,8 @@ #define CONFIG_4xx 1 /* ...member of PPC4xx family */ #define CONFIG_VOM405 1 /* ...on a VOM405 board */ +#define CONFIG_SYS_TEXT_BASE 0xFFFC8000 + #define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f() */ #define CONFIG_MISC_INIT_R 1 /* call misc_init_r() */ @@ -52,7 +38,7 @@ #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ -#define CONFIG_NET_MULTI 1 +#define CONFIG_PPC4xx_EMAC #undef CONFIG_HAS_ETH1 #define CONFIG_MII 1 /* MII PHY management */ @@ -79,8 +65,6 @@ #define CONFIG_CMD_DHCP #define CONFIG_CMD_BSP -#define CONFIG_CMD_PCI -#define CONFIG_CMD_IRQ #define CONFIG_CMD_ELF #define CONFIG_CMD_NAND #define CONFIG_CMD_I2C @@ -103,9 +87,6 @@ #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ #undef CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#ifdef CONFIG_SYS_HUSH_PARSER -#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -#endif #if defined(CONFIG_CMD_KGDB) #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ @@ -123,10 +104,14 @@ #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ +#define CONFIG_CONS_INDEX 2 /* Use UART1 */ +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_serial_clock() + #undef CONFIG_SYS_EXT_SERIAL_CLOCK /* no external serial clock used */ -#define CONFIG_SYS_IGNORE_405_UART_ERRATA_59 /* ignore ppc405gp errata #59 */ #define CONFIG_SYS_BASE_BAUD 691200 -#define CONFIG_UART1_CONSOLE /* define for uart1 as console */ /* The following table includes the supported baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE \ @@ -156,7 +141,6 @@ *----------------------------------------------------------------------- */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define NAND_MAX_CHIPS 1 #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define NAND_BIG_DELAY_US 25 @@ -168,31 +152,6 @@ #define CONFIG_SYS_NAND_SKIP_BAD_DOT_I 1 /* ".i" read skips bad blocks */ #define CONFIG_SYS_NAND_QUIET 1 -/*----------------------------------------------------------------------- - * PCI stuff - *----------------------------------------------------------------------- - */ -#define PCI_HOST_ADAPTER 0 /* configure as pci adapter */ -#define PCI_HOST_FORCE 1 /* configure as pci host */ -#define PCI_HOST_AUTO 2 /* detected via arbiter enable */ - -#define CONFIG_PCI /* include pci support */ -#define CONFIG_PCI_HOST PCI_HOST_HOST /* select pci host function */ -#undef CONFIG_PCI_PNP /* do pci plug-and-play */ - /* resource configuration */ - -#undef CONFIG_PCI_SCAN_SHOW /* print pci devices @ startup */ - -#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x12FE /* PCI Vendor ID: esd gmbh */ -#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0x0405 /* PCI Device ID: CPCI-405 */ -#define CONFIG_SYS_PCI_CLASSCODE 0x0b20 /* PCI Class Code: Processor/PPC*/ -#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */ -#define CONFIG_SYS_PCI_PTM1MS 0xfc000001 /* 64MB, enable hard-wired to 1 */ -#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */ -#define CONFIG_SYS_PCI_PTM2LA 0xffc00000 /* point to flash */ -#define CONFIG_SYS_PCI_PTM2MS 0xffc00001 /* 4MB, enable */ -#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is @@ -223,21 +182,16 @@ #define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ -#if 0 /* test-only */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 /* use for JFFS2 */ -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 /* ! second bank contains U-Boot */ -#endif - /*----------------------------------------------------------------------- * Start addresses for the final memory configuration * (Set up by the startup code) * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 */ #define CONFIG_SYS_SDRAM_BASE 0x00000000 -#define CONFIG_SYS_FLASH_BASE 0xFFFC0000 -#define CONFIG_SYS_MONITOR_BASE TEXT_BASE -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MALLOC_LEN (256 * 1024) /* Reserve 256 kB for malloc() */ +#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_MONITOR_LEN (~(CONFIG_SYS_TEXT_BASE) + 1) +#define CONFIG_SYS_MALLOC_LEN (256 * 1024) #if (CONFIG_SYS_MONITOR_BASE < FLASH_BASE0_PRELIM) # define CONFIG_SYS_RAMBOOT 1 @@ -256,9 +210,11 @@ /*----------------------------------------------------------------------- * I2C EEPROM (CAT24WC16) for environment */ -#define CONFIG_HARD_I2C /* I2c with hardware support */ -#define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed and slave address */ -#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_PPC4XX +#define CONFIG_SYS_I2C_PPC4XX_CH0 +#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 100000 +#define CONFIG_SYS_I2C_PPC4XX_SLAVE_0 0x7F #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* EEPROM CAT28WC08 */ #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */ @@ -292,8 +248,7 @@ /*----------------------------------------------------------------------- * FPGA stuff */ -#define CONFIG_SYS_FPGA_XC95XL 1 /* using Xilinx XC95XL CPLD */ -#define CONFIG_SYS_FPGA_MAX_SIZE 32*1024 /* 32kByte is enough for CPLD */ +#define CONFIG_SYS_XSVF_DEFAULT_ADDR 0xfffc0000 /* FPGA program pin configuration */ #define CONFIG_SYS_FPGA_PRG 0x04000000 /* JTAG TMS pin (ppc output) */ @@ -312,10 +267,9 @@ #define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000 #define CONFIG_SYS_OCM_DATA_SIZE 0x1000 #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */ -#define CONFIG_SYS_INIT_RAM_END CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */ +#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */ -#define CONFIG_SYS_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ -#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE) +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET /*----------------------------------------------------------------------- @@ -334,40 +288,22 @@ /* GPIO Output: OSR=00, ISR=00, TSR=00, TCR=1 */ /* Alt. Funtion Input: OSR=00, ISR=01, TSR=00, TCR=0 */ /* Alt. Funtion Output: OSR=01, ISR=00, TSR=00, TCR=1 */ -#define CONFIG_SYS_GPIO0_OSRH 0x40000500 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_OSRL 0x00000110 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_ISR1H 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_ISR1L 0x14000045 /* 16 ... 31 */ -#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 0 ... 15 */ -#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_OSRL 0x40000500 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_OSRH 0x00000110 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_ISR1L 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_ISR1H 0x14000045 /* 16 ... 31 */ +#define CONFIG_SYS_GPIO0_TSRL 0x00000000 /* 0 ... 15 */ +#define CONFIG_SYS_GPIO0_TSRH 0x00000000 /* 16 ... 31 */ #define CONFIG_SYS_GPIO0_TCR 0xF7FE0014 /* 0 ... 31 */ #define CONFIG_SYS_EEPROM_WP (0x80000000 >> 8) /* GPIO8 */ #define CONFIG_SYS_PLD_RESET (0x80000000 >> 12) /* GPIO12 */ /* - * Internal Definitions - * - * Boot Flags - */ -#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ -#define BOOTFLAG_WARM 0x02 /* Software reboot */ - -/* * Default speed selection (cpu_plb_opb_ebc) in mhz. * This value will be set if iic boot eprom is disabled. */ -#if 0 -#define PLLMR0_DEFAULT PLLMR0_266_133_66_33 -#define PLLMR1_DEFAULT PLLMR1_266_133_66_33 -#endif -#if 0 -#define PLLMR0_DEFAULT PLLMR0_200_100_50_33 -#define PLLMR1_DEFAULT PLLMR1_200_100_50_33 -#endif -#if 1 #define PLLMR0_DEFAULT PLLMR0_133_66_66_33 #define PLLMR1_DEFAULT PLLMR1_133_66_66_33 -#endif #endif /* __CONFIG_H */