X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FC29XPCIE.h;h=b4a51a952835bb9cb9de16d500ef28eb7d5572a7;hb=4862830b696a6d0750e19d32a82553cdb41a85f8;hp=8c664b184d071b8303c7a0e5384dbbdae127ea73;hpb=390194d43fa4478ddb638164ddb114c979f3e57a;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h index 8c664b1..b4a51a9 100644 --- a/include/configs/C29XPCIE.h +++ b/include/configs/C29XPCIE.h @@ -1,7 +1,6 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ /* * Copyright 2013 Freescale Semiconductor, Inc. - * - * SPDX-License-Identifier: GPL-2.0+ */ /* @@ -13,7 +12,6 @@ #ifdef CONFIG_SPIFLASH #define CONFIG_RAMBOOT_SPIFLASH -#define CONFIG_SYS_TEXT_BASE 0x11000000 #define CONFIG_RESET_VECTOR_ADDRESS 0x110bfffc #endif @@ -25,7 +23,7 @@ #define CONFIG_TPL_DRIVERS_MISC_SUPPORT #define CONFIG_SPL_COMMON_INIT_DDR #define CONFIG_SPL_MAX_SIZE (128 << 10) -#define CONFIG_SPL_TEXT_BASE 0xf8f81000 +#define CONFIG_TPL_TEXT_BASE 0xf8f81000 #define CONFIG_SYS_MPC85XX_NO_RESETVEC #define CONFIG_SYS_NAND_U_BOOT_SIZE (832 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST (0x11000000) @@ -35,7 +33,6 @@ #define CONFIG_SPL_INIT_MINIMAL #define CONFIG_SPL_NAND_MINIMAL #define CONFIG_SPL_FLUSH_IMAGE -#define CONFIG_SPL_TEXT_BASE 0xff800000 #define CONFIG_SPL_MAX_SIZE 8192 #define CONFIG_SYS_NAND_U_BOOT_SIZE (128 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST 0xf8f80000 @@ -45,19 +42,16 @@ #define CONFIG_SPL_PAD_TO 0x20000 #define CONFIG_TPL_PAD_TO 0x20000 #define CONFIG_SPL_TARGET "u-boot-with-spl.bin" -#define CONFIG_SYS_TEXT_BASE 0x11001000 #define CONFIG_SYS_LDSCRIPT "arch/powerpc/cpu/mpc85xx/u-boot-nand.lds" #endif -#ifndef CONFIG_SYS_TEXT_BASE -#define CONFIG_SYS_TEXT_BASE 0xeff40000 -#endif - #ifndef CONFIG_RESET_VECTOR_ADDRESS #define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc #endif -#ifdef CONFIG_SPL_BUILD +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SYS_MONITOR_BASE CONFIG_TPL_TEXT_BASE +#elif defined(CONFIG_SPL_BUILD) #define CONFIG_SYS_MONITOR_BASE CONFIG_SPL_TEXT_BASE #else #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ @@ -95,7 +89,6 @@ #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif -#define CONFIG_TSEC_ENET #define CONFIG_ENV_OVERWRITE #define CONFIG_DDR_CLK_FREQ 100000000 @@ -109,7 +102,6 @@ #define CONFIG_L2_CACHE /* toggle L2 cache */ #define CONFIG_BTB /* toggle branch predition */ -#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ #define CONFIG_ENABLE_36BIT_PHYS @@ -118,7 +110,6 @@ #define CONFIG_SYS_MEMTEST_START 0x00200000 #define CONFIG_SYS_MEMTEST_END 0x00400000 -#define CONFIG_PANIC_HANG /* DDR Setup */ #define CONFIG_DDR_SPD @@ -185,10 +176,7 @@ #define CONFIG_SYS_NOR_FTIM3 0x0 /* CFI for NOR Flash */ -#define CONFIG_FLASH_CFI_DRIVER -#define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_EMPTY_INFO -#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* NAND Flash on IFC */ #define CONFIG_NAND_FSL_IFC @@ -288,11 +276,8 @@ #if defined(CONFIG_RAMBOOT_SPIFLASH) #define CONFIG_SYS_RAMBOOT -#define CONFIG_SYS_EXTRA_ENV_RELOC #endif -#define CONFIG_BOARD_EARLY_INIT_R - #define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 @@ -315,7 +300,6 @@ #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #define CONFIG_SPL_RELOC_TEXT_BASE 0xf8f81000 #define CONFIG_SPL_RELOC_STACK (CONFIG_SYS_INIT_L2_ADDR + 128 * 1024) -#define CONFIG_SPL_RELOC_STACK_SIZE (32 << 10) #define CONFIG_SPL_RELOC_MALLOC_ADDR (CONFIG_SYS_INIT_L2_ADDR + 160 * 1024) #define CONFIG_SPL_RELOC_MALLOC_SIZE (96 << 10) #define CONFIG_SPL_GD_ADDR (CONFIG_SYS_INIT_L2_ADDR + 112 * 1024) @@ -342,7 +326,6 @@ #endif /* Serial Port */ -#define CONFIG_CONS_INDEX 1 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) @@ -373,11 +356,8 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 /* eSPI - Enhanced SPI */ -#define CONFIG_SF_DEFAULT_SPEED 10000000 -#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 #ifdef CONFIG_TSEC_ENET -#define CONFIG_MII /* MII PHY management */ #define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "eTSEC1" @@ -399,10 +379,6 @@ */ #if defined(CONFIG_SYS_RAMBOOT) #if defined(CONFIG_RAMBOOT_SPIFLASH) -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_CS 0 -#define CONFIG_ENV_SPI_MAX_HZ 10000000 -#define CONFIG_ENV_SPI_MODE 0 #define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ #define CONFIG_ENV_SECT_SIZE 0x10000 #define CONFIG_ENV_SIZE 0x2000 @@ -428,17 +404,8 @@ /* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_CMDLINE_EDITING /* Command-line editing */ -#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ #define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ - /* * For booting Linux, the board info and command line data * have to be in the first 64 MB of memory, since this is