X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fconfigs%2FAPC405.h;h=1e392290d70623d3727275303fb024aa94296abf;hb=842033e6964e9e5d34aca893c1845416dd8ac2cc;hp=41eaaabfcd3a88c1375d8368bb73e98f6edc0a90;hpb=0d8cb9c04facc029baf4beee5a7e389be343a915;p=platform%2Fkernel%2Fu-boot.git

diff --git a/include/configs/APC405.h b/include/configs/APC405.h
index 41eaaab..1e39229 100644
--- a/include/configs/APC405.h
+++ b/include/configs/APC405.h
@@ -38,6 +38,8 @@
 #define CONFIG_4xx		1	/* ...member of PPC4xx family   */
 #define CONFIG_APCG405		1	/* ...on a APC405 board		*/
 
+#define	CONFIG_SYS_TEXT_BASE	0xFFF80000
+
 #define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f()	*/
 #define CONFIG_BOARD_EARLY_INIT_R 1
 #define CONFIG_MISC_INIT_R      1       /* call misc_init_r()           */
@@ -101,9 +103,9 @@
 #define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
 #define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/
 
-#define CONFIG_NET_MULTI	1
 #undef  CONFIG_HAS_ETH1
 
+#define CONFIG_PPC4xx_EMAC
 #define CONFIG_MII		1	/* MII PHY management		*/
 #define CONFIG_PHY_ADDR		0	/* PHY address			*/
 #define CONFIG_LXT971_NO_SLEEP	1
@@ -175,6 +177,12 @@
 #define CONFIG_SYS_MEMTEST_START	0x0400000 /* memtest works on */
 #define CONFIG_SYS_MEMTEST_END		0x0C00000 /* 4 ... 12 MB in DRAM */
 
+#define CONFIG_CONS_INDEX	1	/* Use UART0			*/
+#define CONFIG_SYS_NS16550
+#define CONFIG_SYS_NS16550_SERIAL
+#define CONFIG_SYS_NS16550_REG_SIZE	1
+#define CONFIG_SYS_NS16550_CLK		get_serial_clock()
+
 #define CONFIG_SYS_EXT_SERIAL_CLOCK    14745600 /* use external serial clock   */
 
 /* The following table includes the supported baudrates */
@@ -210,6 +218,7 @@
 #define PCI_HOST_AUTO		2	/* detected via arbiter enable  */
 
 #define CONFIG_PCI			/* include pci support          */
+#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
 #define CONFIG_PCI_HOST PCI_HOST_FORCE	/* select pci host function     */
 #define CONFIG_PCI_PNP			/* do pci plug-and-play         */
 					/* resource configuration       */
@@ -263,16 +272,10 @@
 /*
  * FLASH organization
  */
-#ifndef __ASSEMBLY__
-extern int flash_banks;
-#endif
-
 #define CONFIG_SYS_FLASH_BASE		0xFE000000
 #define CONFIG_SYS_FLASH_CFI		1	/* Flash is CFI conformant */
 #define CONFIG_FLASH_CFI_DRIVER	1	/* Use the common driver */
 #define CONFIG_SYS_MAX_FLASH_SECT	256	/* max num of sects on one chip */
-#define CONFIG_SYS_MAX_FLASH_BANKS	flash_banks /* max num of flash banks */
-					    /* updated in board_early_init_r */
 #define CONFIG_SYS_MAX_FLASH_BANKS_DETECT 2
 #define CONFIG_SYS_FLASH_QUIET_TEST	1
 #define CONFIG_SYS_FLASH_INCREMENT	0x01000000
@@ -304,6 +307,7 @@ extern int flash_banks;
  * I2C EEPROM (CAT24WC16) for environment
  */
 #define CONFIG_HARD_I2C			/* I2c with hardware support */
+#define CONFIG_PPC4XX_I2C		/* use PPC4xx driver		*/
 #define CONFIG_SYS_I2C_SPEED		100000	/* I2C speed and slave address */
 #define CONFIG_SYS_I2C_SLAVE		0x7F
 
@@ -416,9 +420,8 @@ extern int flash_banks;
 #define CONFIG_SYS_OCM_DATA_SIZE	0x1000
 
 #define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
-#define CONFIG_SYS_INIT_RAM_END	CONFIG_SYS_OCM_DATA_SIZE /* End of used area in RAM */
-#define CONFIG_SYS_GBL_DATA_SIZE	128 /* reserved bytes for initial data */
-#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
+#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
+#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
 /* reserve some memory for BOOT limit info */
 #define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 16)
 
@@ -427,14 +430,6 @@ extern int flash_banks;
 #endif
 
 /*
- * Internal Definitions
- *
- * Boot Flags
- */
-#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
-#define BOOTFLAG_WARM	0x02		/* Software reboot */
-
-/*
  * PCI OHCI controller
  */
 #define CONFIG_USB_OHCI_NEW	1