X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fcommproc.h;h=9d4cb109adde161251a9ae18ac6625ae6b5f9f9d;hb=4a30a93929c112af94b8e00db1382432a69d0809;hp=20637619997e9e297a87783aee88a828b5122492;hpb=544d97e9aa904e489f9e87bae6a6b41cb031cbe9;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/commproc.h b/include/commproc.h index 2063761..9d4cb10 100644 --- a/include/commproc.h +++ b/include/commproc.h @@ -12,15 +12,10 @@ * CPM capabilities. I (or someone else) will add definitions as they * are needed. -- Dan * - * On the MBX board, EPPC-Bug loads CPM microcode into the first 512 - * bytes of the DP RAM and relocates the I2C parameter area to the - * IDMA1 space. The remaining DP RAM is available for buffer descriptors - * or other use. */ #ifndef __CPM_8XX__ #define __CPM_8XX__ -#include #include /* CPM Command register. @@ -56,20 +51,6 @@ /* * DPRAM defines and allocation functions */ - -/* The dual ported RAM is multi-functional. Some areas can be (and are - * being) used for microcode. There is an area that can only be used - * as data ram for buffer descriptors, which is all we use right now. - * Currently the first 512 and last 256 bytes are used for microcode. - */ -#ifdef CONFIG_SYS_ALLOC_DPRAM - -#define CPM_DATAONLY_BASE ((uint)0x0800) -#define CPM_DATAONLY_SIZE ((uint)0x0700) -#define CPM_DP_NOSPACE ((uint)0x7fffffff) - -#else - #define CPM_SERIAL_BASE 0x0800 #define CPM_I2C_BASE 0x0820 #define CPM_SPI_BASE 0x0840 @@ -79,8 +60,6 @@ #define CPM_POST_BASE 0x0980 #define CPM_WLKBD_BASE 0x0a00 -#endif - #ifndef CONFIG_SYS_CPM_POST_WORD_ADDR #define CPM_POST_WORD_ADDR 0x07FC #else @@ -108,7 +87,7 @@ typedef struct cpm_buf_desc { uint cbd_bufaddr; /* Buffer address in host memory */ } cbd_t; -#define BD_SC_EMPTY ((ushort)0x8000) /* Recieve is empty */ +#define BD_SC_EMPTY ((ushort)0x8000) /* Receive is empty */ #define BD_SC_READY ((ushort)0x8000) /* Transmit is ready */ #define BD_SC_WRAP ((ushort)0x2000) /* Last buffer descriptor */ #define BD_SC_INTRPT ((ushort)0x1000) /* Interrupt on change */ @@ -127,6 +106,7 @@ typedef struct cpm_buf_desc { */ #define PROFF_SCC1 ((uint)0x0000) #define PROFF_IIC ((uint)0x0080) +#define PROFF_REVNUM ((uint)0x00b0) #define PROFF_SCC2 ((uint)0x0100) #define PROFF_SPI ((uint)0x0180) #define PROFF_SCC3 ((uint)0x0200) @@ -135,7 +115,6 @@ typedef struct cpm_buf_desc { #define PROFF_SMC2 ((uint)0x0380) /* Define enough so I can at least use the serial port as a UART. - * The MBX uses SMC1 as the host serial port. */ typedef struct smc_uart { ushort smc_rbase; /* Rx Buffer descriptor base address */ @@ -434,71 +413,6 @@ typedef struct scc_enet { * #define FEC_ENET to enable the SCC resp. FEC ethernet drivers. **********************************************************************/ - -/*** ADS *************************************************************/ - -#if defined(CONFIG_MPC860) && defined(CONFIG_ADS) -/* This ENET stuff is for the MPC860ADS with ethernet on SCC1. - */ - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) - -#define PB_ENET_TENA ((uint)0x00001000) - -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) - -/* 68160 PHY control */ - -#define PC_ENET_ETHLOOP ((ushort)0x0800) -#define PC_ENET_TPFLDL ((ushort)0x0400) -#define PC_ENET_TPSQEL ((ushort)0x0200) - -#endif /* MPC860ADS */ - -/*** AMX860 **********************************************/ - -#if defined(CONFIG_AMX860) - -/* This ENET stuff is for the AMX860 with ethernet on SCC1. - */ - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0800) - -#define PB_ENET_TENA ((uint)0x00001000) - -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003e) - -/* 68160 PHY control */ - -#define PB_ENET_ETHLOOP ((uint)0x00020000) -#define PB_ENET_TPFLDL ((uint)0x00010000) -#define PB_ENET_TPSQEL ((uint)0x00008000) -#define PD_ENET_ETH_EN ((ushort)0x0004) - -#endif /* CONFIG_AMX860 */ - /*** BSEIP **********************************************************/ #ifdef CONFIG_BSEIP @@ -526,239 +440,38 @@ typedef struct scc_enet { #define SICR_ENET_CLKRT ((uint)0x00002c00) #endif /* CONFIG_BSEIP */ -/*** BSEIP **********************************************************/ - -#ifdef CONFIG_FLAGADM -/* Enet configuration for the FLAGADM */ -/* Enet on SCC2 */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0400) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003400) -#endif /* CONFIG_FLAGADM */ - -/*** C2MON **********************************************************/ - -#ifdef CONFIG_C2MON - -# ifndef CONFIG_FEC_ENET /* use SCC for 10Mbps Ethernet */ -# error "Ethernet on SCC not supported on C2MON Board!" -# else /* Use FEC for Fast Ethernet */ - -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_C2MON */ - -/*********************************************************************/ - - -/*** CCM ***********************************************************/ - -/* The CCM uses the FEC on a MPC860T for Ethernet */ - -#if defined(CONFIG_CCM) - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_CCM */ - -/*** ELPT860 *********************************************************/ - -#ifdef CONFIG_ELPT860 -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -# define PROFF_ENET PROFF_SCC1 -# define CPM_CR_ENET CPM_CR_CH_SCC1 -# define SCC_ENET 0 - -# define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -# define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -# define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -# define PA_ENET_TCLK ((ushort)0x0200) /* PA 6 */ - -# define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -# define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -# define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -# define SICR_ENET_MASK ((uint)0x000000FF) -# define SICR_ENET_CLKRT ((uint)0x00000025) -#endif /* CONFIG_ELPT860 */ - -/*** ESTEEM 192E **************************************************/ -#ifdef CONFIG_ESTEEM192E -/* ESTEEM192E - * This ENET stuff is for the MPC850 with ethernet on SCC2. This - * is very similar to the RPX-Lite configuration. - * Note TENA , LOOPBACK , FDPLEX_DIS on Port B. - */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) - -#define PB_ENET_LOOPBACK ((uint)0x00004000) -#define PB_ENET_FDPLEX_DIS ((uint)0x00008000) - -#endif - -/*** FADS823 ********************************************************/ - -#if defined(CONFIG_MPC823FADS) && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC823FADS with ethernet on SCC2. - */ -#ifdef CONFIG_SCC2_ENET -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define CPMVEC_ENET CPMVEC_SCC2 -#endif - -#ifdef CONFIG_SCC1_ENET -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define CPMVEC_ENET CPMVEC_SCC1 -#endif - -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0200) - -#define PB_ENET_TENA ((uint)0x00002000) - -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) - -#endif /* CONFIG_FADS823FADS */ - -/*** FADS850SAR ********************************************************/ - -#if defined(CONFIG_MPC850SAR) && defined(CONFIG_FADS) -/* This ENET stuff is for the MPC850SAR with ethernet on SCC2. Some of - * this may be unique to the FADS850SAR configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) /* RCLK-CLK2, TCLK-CLK4 */ -#endif /* CONFIG_FADS850SAR */ - -/*** FADS860T********************************************************/ - -#if defined(CONFIG_FADS) && defined(CONFIG_MPC86x) -/* - * This ENET stuff is for the MPC86xFADS/MPC8xxADS with ethernet on SCC1. - */ -#ifdef CONFIG_SCC1_ENET - -#define SCC_ENET 0 - -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 - -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0100) -#define PA_ENET_RCLK ((ushort)0x0200) +/*** KM8XX *********************************************************/ -#define PB_ENET_TENA ((uint)0x00001000) +/* The KM8XX Service Module uses SCC3 for Ethernet */ -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) +#ifdef CONFIG_KM8XX +#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ +#define CPM_CR_ENET CPM_CR_CH_SCC3 +#define SCC_ENET 2 +#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ +#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ +#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ +#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002c) +#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ -#endif /* CONFIG_SCC1_ETHERNET */ +#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ +#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ -/* - * This ENET stuff is for the MPC860TFADS/MPC86xADS/MPC885ADS - * with ethernet on FEC. +/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to + * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. */ +#define SICR_ENET_MASK ((uint)0x00FF0000) +#define SICR_ENET_CLKRT ((uint)0x00250000) +#endif /* CONFIG_KM8XX */ -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* Use FEC for Ethernet */ -#endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_FADS && CONFIG_MPC86x */ +/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, R360MPI **********/ -/*** FPS850L, FPS860L ************************************************/ +#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ + defined(CONFIG_TQM823L) || \ + defined(CONFIG_TQM823M) || defined(CONFIG_TQM850L) || \ + defined(CONFIG_TQM850M) || defined(CONFIG_TQM885D) -#if defined(CONFIG_FPS850L) || defined(CONFIG_FPS860L) /* Bits in parallel I/O port registers that have to be set/cleared * to configure the pins for SCC2 use. */ @@ -770,715 +483,58 @@ typedef struct scc_enet { #define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ #define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PC_ENET_TENA ((ushort)0x0002) /* PC 14 */ +#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ + #define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ #define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. */ #define SICR_ENET_MASK ((uint)0x0000ff00) #define SICR_ENET_CLKRT ((uint)0x00002600) -#endif /* CONFIG_FPS850L, CONFIG_FPS860L */ - -/*** GEN860T **********************************************************/ -#if defined(CONFIG_GEN860T) -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3-15 */ -#endif /* CONFIG_GEN860T */ - -/*** GENIETV ********************************************************/ - -#if defined(CONFIG_GENIETV) -/* Ethernet is only on SCC2 */ - -#define CONFIG_SCC2_ENET -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define CPMVEC_ENET CPMVEC_SCC2 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ +# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ +#define FEC_ENET +# endif /* CONFIG_FEC_ENET */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ +#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ +/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) +#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ + defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ + defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ + defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) + +# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ -#endif /* CONFIG_GENIETV */ +/* Bits in parallel I/O port registers that have to be set/cleared + * to configure the pins for SCC1 use. + */ +#define PROFF_ENET PROFF_SCC1 +#define CPM_CR_ENET CPM_CR_CH_SCC1 +#define SCC_ENET 0 +#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ +#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ +#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ +#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -/*** HERMES-PRO ******************************************************/ +#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ +#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ +#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ -/* The HERMES-PRO uses the FEC on a MPC860T for Ethernet */ +/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to + * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. + */ +#define SICR_ENET_MASK ((uint)0x000000ff) +#define SICR_ENET_CLKRT ((uint)0x00000026) -#ifdef CONFIG_HERMES +# endif /* CONFIG_SCC1_ENET */ -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET +# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_HERMES */ - -/*** IAD210 **********************************************************/ - -/* The IAD210 uses the FEC on a MPC860P for Ethernet */ - -#if defined(CONFIG_IAD210) - -# define FEC_ENET /* use FEC for Ethernet */ -# undef SCC_ENET - -# define PD_MII_TXD1 ((ushort) 0x1000 ) /* PD 3 */ -# define PD_MII_TXD2 ((ushort) 0x0800 ) /* PD 4 */ -# define PD_MII_TXD3 ((ushort) 0x0400 ) /* PD 5 */ -# define PD_MII_RX_DV ((ushort) 0x0200 ) /* PD 6 */ -# define PD_MII_RX_ERR ((ushort) 0x0100 ) /* PD 7 */ -# define PD_MII_RX_CLK ((ushort) 0x0080 ) /* PD 8 */ -# define PD_MII_TXD0 ((ushort) 0x0040 ) /* PD 9 */ -# define PD_MII_RXD0 ((ushort) 0x0020 ) /* PD 10 */ -# define PD_MII_TX_ERR ((ushort) 0x0010 ) /* PD 11 */ -# define PD_MII_MDC ((ushort) 0x0008 ) /* PD 12 */ -# define PD_MII_RXD1 ((ushort) 0x0004 ) /* PD 13 */ -# define PD_MII_RXD2 ((ushort) 0x0002 ) /* PD 14 */ -# define PD_MII_RXD3 ((ushort) 0x0001 ) /* PD 15 */ - -# define PD_MII_MASK ((ushort) 0x1FFF ) /* PD 3...15 */ - -#endif /* CONFIG_IAD210 */ - -/*** ICU862 **********************************************************/ - -#if defined(CONFIG_ICU862) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_ICU862 */ - -/*** IP860 **********************************************************/ - -#if defined(CONFIG_IP860) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0100) /* PA 7 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -#define PB_ENET_RESET (uint)0x00000008 /* PB 28 */ -#define PB_ENET_JABD (uint)0x00000004 /* PB 29 */ - -/* Control bits in the SICR to route TCLK (CLK1) and RCLK (CLK2) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000002C) -#endif /* CONFIG_IP860 */ - -/*** IVMS8 **********************************************************/ - -/* The IVMS8 uses the FEC on a MPC860T for Ethernet */ - -#if defined(CONFIG_IVMS8) || defined(CONFIG_IVML24) - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - -#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ - -#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_IVMS8, CONFIG_IVML24 */ - -/*** KUP4K, KUP4X ****************************************************/ -/* The KUP4 boards uses the FEC on a MPC8xx for Ethernet */ - -#if defined(CONFIG_KUP4K) || defined(CONFIG_KUP4X) - -#define FEC_ENET /* use FEC for EThernet */ -#undef SCC_ENET - -#define PB_ENET_POWER ((uint)0x00010000) /* PB 15 */ - -#define PC_ENET_RESET ((ushort)0x0010) /* PC 11 */ - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -#endif /* CONFIG_KUP4K */ - - -/*** LANTEC *********************************************************/ - -#if defined(CONFIG_LANTEC) && CONFIG_LANTEC >= 2 -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_LBK ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000FF00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) -#endif /* CONFIG_LANTEC v2 */ - -/*** LWMON **********************************************************/ - -#if defined(CONFIG_LWMON) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0800) /* PA 4 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK4) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003E00) -#endif /* CONFIG_LWMON */ - -/*** NX823 ***********************************************/ - -#if defined(CONFIG_NX823) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) - -#endif /* CONFIG_NX823 */ - -/*** MBX ************************************************************/ - -#ifdef CONFIG_MBX -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. The TCLK and RCLK seem unique - * to the MBX860 board. Any two of the four available clocks could be - * used, and the MPC860 cookbook manual has an example using different - * clock pins. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PC_ENET_TENA ((ushort)0x0001) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) -#endif /* CONFIG_MBX */ - -/*** KM8XX *********************************************************/ - -/* The KM8XX Service Module uses SCC3 for Ethernet */ - -#ifdef CONFIG_KM8XX -#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define SCC_ENET 2 -#define PA_ENET_RXD ((ushort)0x0010) /* PA 11 */ -#define PA_ENET_TXD ((ushort)0x0020) /* PA 10 */ -#define PA_ENET_RCLK ((ushort)0x1000) /* PA 3 CLK 5 */ -#define PA_ENET_TCLK ((ushort)0x2000) /* PA 2 CLK 6 */ - -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0200) /* PC 6 */ -#define PC_ENET_CLSN ((ushort)0x0100) /* PC 7 */ - -/* Control bits in the SICR to route TCLK (CLK6) and RCLK (CLK5) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00250000) -#endif /* CONFIG_KM8XX */ - - -/*** MHPC ********************************************************/ - -#if defined(CONFIG_MHPC) -/* This ENET stuff is for the MHPC with ethernet on SCC2. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) /* RCLK-CLK2, TCLK-CLK3 */ -#endif /* CONFIG_MHPC */ - -/*** NETVIA *******************************************************/ - -/* SinoVee Microsystems SC8xx series FEL8xx-AT,SC823,SC850,SC855T,SC860T */ -#if ( defined CONFIG_SVM_SC8xx ) -# ifndef CONFIG_FEC_ENET - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - - /* Bits in parallel I/O port registers that have to be set/cleared - * * * * to configure the pins for SCC2 use. - * * * */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0400) /* PA 5 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * * * * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - * * * */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003700) - -# else /* Use FEC for Fast Ethernet */ - -#undef SCC_ENET -#define FEC_ENET - -#define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ -#define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ -#define PD_MII_TXD3 ((ushort)0x0400) /* PD 5 */ -#define PD_MII_RX_DV ((ushort)0x0200) /* PD 6 */ -#define PD_MII_RX_ERR ((ushort)0x0100) /* PD 7 */ -#define PD_MII_RX_CLK ((ushort)0x0080) /* PD 8 */ -#define PD_MII_TXD0 ((ushort)0x0040) /* PD 9 */ -#define PD_MII_RXD0 ((ushort)0x0020) /* PD 10 */ -#define PD_MII_TX_ERR ((ushort)0x0010) /* PD 11 */ -#define PD_MII_MDC ((ushort)0x0008) /* PD 12 */ -#define PD_MII_RXD1 ((ushort)0x0004) /* PD 13 */ -#define PD_MII_RXD2 ((ushort)0x0002) /* PD 14 */ -#define PD_MII_RXD3 ((ushort)0x0001) /* PD 15 */ - -#define PD_MII_MASK ((ushort)0x1FFF) /* PD 3...15 */ - -# endif /* CONFIG_FEC_ENET */ -#endif /* CONFIG_SVM_SC8xx */ - - -#if defined(CONFIG_NETVIA) -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA 4 */ - -#if !defined(CONFIG_NETVIA_VERSION) || CONFIG_NETVIA_VERSION == 1 -# define PB_ENET_PDN ((ushort)0x4000) /* PB 17 */ -#elif CONFIG_NETVIA_VERSION >= 2 -# define PC_ENET_PDN ((ushort)0x0008) /* PC 12 */ -#endif - -#define PB_ENET_TENA ((ushort)0x2000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002f00) - -#endif /* CONFIG_NETVIA */ - -/*** QS850/QS823 ***************************************************/ - -#if defined(CONFIG_QS850) || defined(CONFIG_QS823) -#undef FEC_ENET /* Don't use FEC for EThernet */ - -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 - -#define PA_ENET_RXD ((ushort)0x0004) /* RXD on PA13 (Pin D9) */ -#define PA_ENET_TXD ((ushort)0x0008) /* TXD on PA12 (Pin D7) */ -#define PC_ENET_RENA ((ushort)0x0080) /* RENA on PC8 (Pin D12) */ -#define PC_ENET_CLSN ((ushort)0x0040) /* CLSN on PC9 (Pin C12) */ -#define PA_ENET_TCLK ((ushort)0x0200) /* TCLK on PA6 (Pin D8) */ -#define PA_ENET_RCLK ((ushort)0x0800) /* RCLK on PA4 (Pin D10) */ -#define PB_ENET_TENA ((uint)0x00002000) /* TENA on PB18 (Pin D11) */ -#define PC_ENET_LBK ((ushort)0x0010) /* Loopback control on PC11 (Pin B14) */ -#define PC_ENET_LI ((ushort)0x0020) /* Link Integrity control PC10 (A15) */ -#define PC_ENET_SQE ((ushort)0x0100) /* SQE Disable control PC7 (B15) */ - -/* SCC2 TXCLK from CLK2 - * SCC2 RXCLK from CLK4 - * SCC2 Connected to NMSI */ -#define SICR_ENET_MASK ((uint)0x00007F00) -#define SICR_ENET_CLKRT ((uint)0x00003D00) - -#endif /* CONFIG_QS850/QS823 */ - -/*** QS860T ***************************************************/ - -#ifdef CONFIG_QS860T -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for EThernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -/* This ENET stuff is for GTH 10 Mbit ( SCC ) */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 - -#define PA_ENET_RXD ((ushort)0x0001) /* PA15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA14 */ -#define PA_ENET_TCLK ((ushort)0x0800) /* PA4 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA6 */ -#define PB_ENET_TENA ((uint)0x00001000) /* PB19 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC10 */ - -#define SICR_ENET_MASK ((uint)0x000000ff) -/* RCLK PA4 -->CLK4, TCLK PA6 -->CLK2 */ -#define SICR_ENET_CLKRT ((uint)0x0000003D) - -#endif /* CONFIG_QS860T */ - -/*** RPXCLASSIC *****************************************************/ - -#ifdef CONFIG_RPXCLASSIC - -#ifdef CONFIG_FEC_ENET - -# define FEC_ENET /* use FEC for EThernet */ -# undef SCC_ENET - -#else /* ! CONFIG_FEC_ENET */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) -#define PA_ENET_TXD ((ushort)0x0002) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#define PB_ENET_TENA ((uint)0x00001000) -#define PC_ENET_CLSN ((ushort)0x0010) -#define PC_ENET_RENA ((ushort)0x0020) - -/* Control bits in the SICR to route TCLK (CLK2) and RCLK (CLK4) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x0000003d) - -#endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_RPXCLASSIC */ - -/*** RPXLITE ********************************************************/ - -#ifdef CONFIG_RPXLITE -/* This ENET stuff is for the MPC850 with ethernet on SCC2. Some of - * this may be unique to the RPX-Lite configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0200) -#define PA_ENET_RCLK ((ushort)0x0800) -#if defined(CONFIG_RMU) -#define PC_ENET_TENA ((uint)0x00000002) /* PC14 */ -#else -#define PB_ENET_TENA ((uint)0x00002000) -#endif -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00003d00) -#endif /* CONFIG_RPXLITE */ - -/*** SM850 *********************************************************/ - -/* The SM850 Service Module uses SCC2 for IrDA and SCC3 for Ethernet */ - -#ifdef CONFIG_SM850 -#define PROFF_ENET PROFF_SCC3 /* Ethernet on SCC3 */ -#define CPM_CR_ENET CPM_CR_CH_SCC3 -#define SCC_ENET 2 -#define PB_ENET_RXD ((uint)0x00000004) /* PB 29 */ -#define PB_ENET_TXD ((uint)0x00000002) /* PB 30 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ -#define PC_ENET_TENA ((ushort)0x0004) /* PC 13 */ - -#define PC_ENET_RENA ((ushort)0x0800) /* PC 4 */ -#define PC_ENET_CLSN ((ushort)0x0400) /* PC 5 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC3. Also, make sure GR3 (bit 8) and SC3 (bit 9) are zero. - */ -#define SICR_ENET_MASK ((uint)0x00FF0000) -#define SICR_ENET_CLKRT ((uint)0x00260000) -#endif /* CONFIG_SM850 */ - -/*** SPD823TS ******************************************************/ - -#ifdef CONFIG_SPD823TS -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 /* Ethernet on SCC2 */ -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_MDC ((ushort)0x0001) /* PA 15 !!! */ -#define PA_ENET_MDIO ((ushort)0x0002) /* PA 14 !!! */ -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0200) /* PA 6 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -#define PC_ENET_RESET ((ushort)0x0100) /* PC 7 !!! */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK2) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002E00) -#endif /* CONFIG_SPD823TS */ - -/*** SXNI855T ******************************************************/ - -#if defined(CONFIG_SXNI855T) - -#ifdef CONFIG_FEC_ENET -#define FEC_ENET /* use FEC for Ethernet */ -#endif /* CONFIG_FEC_ETHERNET */ - -#endif /* CONFIG_SXNI855T */ - -/*** MVS1, TQM823L/M, TQM850L/M, TQM885D, ETX094, R360MPI **********/ - -#if (defined(CONFIG_MVS) && CONFIG_MVS < 2) || \ - defined(CONFIG_R360MPI) || defined(CONFIG_RBC823) || \ - defined(CONFIG_TQM823L) || defined(CONFIG_TQM823M) || \ - defined(CONFIG_TQM850L) || defined(CONFIG_TQM850M) || \ - defined(CONFIG_TQM885D) || defined(CONFIG_ETX094) || \ - defined(CONFIG_RRVISION)|| defined(CONFIG_VIRTLAB2)|| \ - (defined(CONFIG_LANTEC) && CONFIG_LANTEC < 2) - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC2 use. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#if (!defined(CONFIG_TK885D)) /* TK885D does not use SCC Ethernet */ -#define SCC_ENET 1 -#endif -#define PA_ENET_RXD ((ushort)0x0004) /* PA 13 */ -#define PA_ENET_TXD ((ushort)0x0008) /* PA 12 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PB_ENET_TENA ((uint)0x00002000) /* PB 18 */ - -#define PC_ENET_CLSN ((ushort)0x0040) /* PC 9 */ -#define PC_ENET_RENA ((ushort)0x0080) /* PC 8 */ -#if defined(CONFIG_R360MPI) -#define PC_ENET_LBK ((ushort)0x0008) /* PC 12 */ -#endif /* CONFIG_R360MPI */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC2. Also, make sure GR2 (bit 16) and SC2 (bit 17) are zero. - */ -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002600) - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ -#define FEC_ENET -# endif /* CONFIG_FEC_ENET */ - -#endif /* CONFIG_MVS v1, CONFIG_TQM823L/M, CONFIG_TQM850L/M, etc. */ - -/*** TQM855L/M, TQM860L/M, TQM862L/M, TQM866L/M *********************/ - -#if defined(CONFIG_TQM855L) || defined(CONFIG_TQM855M) || \ - defined(CONFIG_TQM860L) || defined(CONFIG_TQM860M) || \ - defined(CONFIG_TQM862L) || defined(CONFIG_TQM862M) || \ - defined(CONFIG_TQM866L) || defined(CONFIG_TQM866M) - -# ifdef CONFIG_SCC1_ENET /* use SCC for 10Mbps Ethernet */ - -/* Bits in parallel I/O port registers that have to be set/cleared - * to configure the pins for SCC1 use. - */ -#define PROFF_ENET PROFF_SCC1 -#define CPM_CR_ENET CPM_CR_CH_SCC1 -#define SCC_ENET 0 -#define PA_ENET_RXD ((ushort)0x0001) /* PA 15 */ -#define PA_ENET_TXD ((ushort)0x0002) /* PA 14 */ -#define PA_ENET_RCLK ((ushort)0x0100) /* PA 7 */ -#define PA_ENET_TCLK ((ushort)0x0400) /* PA 5 */ - -#define PC_ENET_TENA ((ushort)0x0001) /* PC 15 */ -#define PC_ENET_CLSN ((ushort)0x0010) /* PC 11 */ -#define PC_ENET_RENA ((ushort)0x0020) /* PC 10 */ - -/* Control bits in the SICR to route TCLK (CLK3) and RCLK (CLK1) to - * SCC1. Also, make sure GR1 (bit 24) and SC1 (bit 25) are zero. - */ -#define SICR_ENET_MASK ((uint)0x000000ff) -#define SICR_ENET_CLKRT ((uint)0x00000026) - -# endif /* CONFIG_SCC1_ENET */ - -# ifdef CONFIG_FEC_ENET /* Use FEC for Fast Ethernet */ - -#define FEC_ENET +#define FEC_ENET #define PD_MII_TXD1 ((ushort)0x1000) /* PD 3 */ #define PD_MII_TXD2 ((ushort)0x0800) /* PD 4 */ @@ -1499,29 +555,6 @@ typedef struct scc_enet { # endif /* CONFIG_FEC_ENET */ #endif /* CONFIG_TQM855L/M, TQM860L/M, TQM862L/M */ -/*** V37 **********************************************************/ - -#ifdef CONFIG_V37 -/* This ENET stuff is for the MPC823 with ethernet on SCC2. Some of - * this may be unique to the Marel V37 configuration. - * Note TENA is on Port B. - */ -#define PROFF_ENET PROFF_SCC2 -#define CPM_CR_ENET CPM_CR_CH_SCC2 -#define SCC_ENET 1 -#define PA_ENET_RXD ((ushort)0x0004) -#define PA_ENET_TXD ((ushort)0x0008) -#define PA_ENET_TCLK ((ushort)0x0400) -#define PA_ENET_RCLK ((ushort)0x0200) -#define PB_ENET_TENA ((uint)0x00002000) -#define PC_ENET_CLSN ((ushort)0x0040) -#define PC_ENET_RENA ((ushort)0x0080) - -#define SICR_ENET_MASK ((uint)0x0000ff00) -#define SICR_ENET_CLKRT ((uint)0x00002e00) -#endif /* CONFIG_V37 */ - - /*********************************************************************/ /* SCC Event register as used by Ethernet.