X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=include%2Fasm-avr32%2Farch-at32ap700x%2Fclk.h;h=7817572270c1245095d12b81c62e0f0330d0ac61;hb=6d0f6bcf337c5261c08fabe12982178c2c489d76;hp=4a1dd33b56b0c259b7bbebb91ef8e5a9ae02524c;hpb=7a68389a231ac061ba2ffd628f86e15ed0545a7b;p=platform%2Fkernel%2Fu-boot.git diff --git a/include/asm-avr32/arch-at32ap700x/clk.h b/include/asm-avr32/arch-at32ap700x/clk.h index 4a1dd33..7817572 100644 --- a/include/asm-avr32/arch-at32ap700x/clk.h +++ b/include/asm-avr32/arch-at32ap700x/clk.h @@ -25,26 +25,26 @@ #include #ifdef CONFIG_PLL -#define MAIN_CLK_RATE ((CFG_OSC0_HZ / CFG_PLL0_DIV) * CFG_PLL0_MUL) +#define MAIN_CLK_RATE ((CONFIG_SYS_OSC0_HZ / CONFIG_SYS_PLL0_DIV) * CONFIG_SYS_PLL0_MUL) #else -#define MAIN_CLK_RATE (CFG_OSC0_HZ) +#define MAIN_CLK_RATE (CONFIG_SYS_OSC0_HZ) #endif static inline unsigned long get_cpu_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_CPU; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_CPU; } static inline unsigned long get_hsb_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_HSB; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB; } static inline unsigned long get_pba_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_PBA; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBA; } static inline unsigned long get_pbb_clk_rate(void) { - return MAIN_CLK_RATE >> CFG_CLKDIV_PBB; + return MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_PBB; } /* Accessors for specific devices. More will be added as needed. */ @@ -74,10 +74,17 @@ static inline unsigned long get_mci_clk_rate(void) return get_pbb_clk_rate(); } #endif +#ifdef AT32AP700x_CHIP_HAS_SPI +static inline unsigned long get_spi_clk_rate(unsigned int dev_id) +{ + return get_pba_clk_rate(); +} +#endif extern void clk_init(void); +extern void gclk_init(void) __attribute__((weak)); /* Board code may need the SDRAM base clock as a compile-time constant */ -#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CFG_CLKDIV_HSB) +#define SDRAMC_BUS_HZ (MAIN_CLK_RATE >> CONFIG_SYS_CLKDIV_HSB) #endif /* __ASM_AVR32_ARCH_CLK_H__ */