X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=gdb%2Fxtensa-tdep.h;h=d7ba5628e42a583b4b0fadba9d06ba570f3ea949;hb=50c8a5160c5292ec7fbf1817960d58b15cb6fc5f;hp=3f8b8cb5417d4459a6283dbba0d5272ecdebd758;hpb=304fe2552d6e0821e8fdb7575f8e7ba6607a076d;p=platform%2Fupstream%2Fbinutils.git diff --git a/gdb/xtensa-tdep.h b/gdb/xtensa-tdep.h index 3f8b8cb..d7ba562 100644 --- a/gdb/xtensa-tdep.h +++ b/gdb/xtensa-tdep.h @@ -1,6 +1,6 @@ /* Target-dependent code for the Xtensa port of GDB, the GNU debugger. - Copyright (C) 2003, 2005, 2006, 2007 Free Software Foundation, Inc. + Copyright (C) 2003-2014 Free Software Foundation, Inc. This file is part of GDB. @@ -42,7 +42,7 @@ typedef enum /* Xtensa register group. */ -#define XTENSA_MAX_COPROCESSOR 0x08 /* Number of Xtensa coprocessors. */ +#define XTENSA_MAX_COPROCESSOR 0x10 /* Number of Xtensa coprocessors. */ typedef enum { @@ -59,6 +59,7 @@ typedef enum xtRegisterGroupVectra = 0x0800, /* Vectra. */ xtRegisterGroupSystem = 0x1000, /* System. */ + xtRegisterGroupNCP = 0x00800000, /* Non-CP non-base opt/custom. */ xtRegisterGroupCP0 = 0x01000000, /* CP0. */ xtRegisterGroupCP1 = 0x02000000, /* CP1. */ xtRegisterGroupCP2 = 0x04000000, /* CP2. */ @@ -80,34 +81,27 @@ typedef enum } xtensa_target_flags_t; -/* Xtensa ELF core file register set representation ('.reg' section). +/* Xtensa ELF core file register set representation ('.reg' section). Copied from target-side ELF header . */ -typedef unsigned long xtensa_elf_greg_t; +typedef uint32_t xtensa_elf_greg_t; typedef struct { - xtensa_elf_greg_t xchal_config_id0; - xtensa_elf_greg_t xchal_config_id1; - xtensa_elf_greg_t cpux; - xtensa_elf_greg_t cpuy; xtensa_elf_greg_t pc; xtensa_elf_greg_t ps; - xtensa_elf_greg_t exccause; - xtensa_elf_greg_t excvaddr; - xtensa_elf_greg_t windowbase; - xtensa_elf_greg_t windowstart; xtensa_elf_greg_t lbeg; xtensa_elf_greg_t lend; xtensa_elf_greg_t lcount; xtensa_elf_greg_t sar; - xtensa_elf_greg_t syscall; - xtensa_elf_greg_t ar[0]; /* variable size (per config). */ + xtensa_elf_greg_t windowstart; + xtensa_elf_greg_t windowbase; + xtensa_elf_greg_t reserved[8+48]; + xtensa_elf_greg_t ar[64]; } xtensa_elf_gregset_t; -#define SIZEOF_GREGSET (sizeof (xtensa_elf_gregset_t) + gdbarch_tdep (current_gdbarch)->num_aregs * 4) -#define XTENSA_ELF_NGREG (SIZEOF_GREGSET / sizeof(xtensa_elf_greg_t)) - +#define XTENSA_ELF_NGREG (sizeof (xtensa_elf_gregset_t) \ + / sizeof (xtensa_elf_greg_t)) /* Mask. */ @@ -141,19 +135,24 @@ typedef struct unsigned int target_number; /* Register target number. */ int flags; /* Flags. */ + int coprocessor; /* Coprocessor num, -1 for non-CP, else -2. */ const xtensa_mask_t *mask; /* Register is a compilation of other regs. */ const char *fetch; /* Instruction sequence to fetch register. */ const char *store; /* Instruction sequence to store register. */ } xtensa_register_t; +/* For xtensa-config.c to expand to the structure above. */ +#define XTREG(index,ofs,bsz,sz,al,tnum,flg,cp,ty,gr,name,fet,sto,mas,ct,x,y) \ + {#name, ofs, ty, ((gr) | ((xtRegisterGroupNCP >> 2) << (cp + 2))), \ + ct, bsz, sz, al, tnum, flg, cp, mas, fet, sto}, +#define XTREG_END {0, 0, 0, 0, 0, 0, 0, 0, -1, 0, 0, 0, 0, 0}, -#define XTENSA_REGISTER_FLAGS_PRIVILEDGED 0x0001 +#define XTENSA_REGISTER_FLAGS_PRIVILEGED 0x0001 #define XTENSA_REGISTER_FLAGS_READABLE 0x0002 #define XTENSA_REGISTER_FLAGS_WRITABLE 0x0004 #define XTENSA_REGISTER_FLAGS_VOLATILE 0x0008 - /* Call-ABI for stack frame. */ typedef enum @@ -197,7 +196,8 @@ struct gdbarch_tdep xtensa_register_t* regmap; - unsigned int num_regs; /* Number of registers in regmap. */ + unsigned int num_regs; /* Number of registers in register map. */ + unsigned int num_nopriv_regs; /* Number of non-privileged registers. */ unsigned int num_pseudo_regs; /* Number of pseudo registers. */ unsigned int num_aregs; /* Size of register file. */ unsigned int num_contexts; @@ -226,9 +226,75 @@ struct gdbarch_tdep unsigned long *fp_layout; /* Layout of custom/TIE regs in 'FP' area. */ unsigned int fp_layout_bytes; /* Size of layout information (in bytes). */ unsigned long *gregmap; -}; + /* Cached register types. */ + struct ctype_cache + { + struct ctype_cache *next; + int size; + struct type *virtual_type; + } *type_entries; +}; +/* Macro to instantiate a gdbarch_tdep structure. */ + +#define XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spillsz) \ + { \ + .target_flags = 0, \ + .spill_location = -1, \ + .spill_size = (spillsz), \ + .unused = 0, \ + .call_abi = 0, \ + .debug_interrupt_level = XCHAL_DEBUGLEVEL, \ + .icache_line_bytes = XCHAL_ICACHE_LINESIZE, \ + .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ + .dcache_writeback = XCHAL_DCACHE_IS_WRITEBACK, \ + .isa_use_windowed_registers = (XSHAL_ABI != XTHAL_ABI_CALL0), \ + .isa_use_density_instructions = XCHAL_HAVE_DENSITY, \ + .isa_use_exceptions = XCHAL_HAVE_EXCEPTIONS, \ + .isa_use_ext_l32r = XSHAL_USE_ABSOLUTE_LITERALS, \ + .isa_max_insn_size = XCHAL_MAX_INSTRUCTION_SIZE, \ + .debug_num_ibreaks = XCHAL_NUM_IBREAK, \ + .debug_num_dbreaks = XCHAL_NUM_DBREAK, \ + .regmap = rmap, \ + .num_regs = 0, \ + .num_nopriv_regs = 0, \ + .num_pseudo_regs = 0, \ + .num_aregs = XCHAL_NUM_AREGS, \ + .num_contexts = XCHAL_NUM_CONTEXTS, \ + .ar_base = -1, \ + .a0_base = -1, \ + .wb_regnum = -1, \ + .ws_regnum = -1, \ + .pc_regnum = -1, \ + .ps_regnum = -1, \ + .lbeg_regnum = -1, \ + .lend_regnum = -1, \ + .lcount_regnum = -1, \ + .sar_regnum = -1, \ + .litbase_regnum = -1, \ + .interrupt_regnum = -1, \ + .interrupt2_regnum = -1, \ + .cpenable_regnum = -1, \ + .debugcause_regnum = -1, \ + .exccause_regnum = -1, \ + .excvaddr_regnum = -1, \ + .max_register_raw_size = 0, \ + .max_register_virtual_size = 0, \ + .fp_layout = 0, \ + .fp_layout_bytes = 0, \ + .gregmap = 0, \ + } +#define XTENSA_CONFIG_INSTANTIATE(rmap,spill_size) \ + struct gdbarch_tdep xtensa_tdep = \ + XTENSA_GDBARCH_TDEP_INSTANTIATE(rmap,spill_size); + +#ifndef XCHAL_NUM_CONTEXTS +#define XCHAL_NUM_CONTEXTS 0 +#endif +#ifndef XCHAL_HAVE_EXCEPTIONS +#define XCHAL_HAVE_EXCEPTIONS 1 +#endif #define WB_SHIFT 2 /* We assign fixed numbers to the registers of the "current" window