X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fvideo%2Frockchip%2Frk_edp.c;h=99b16cd95edc021fe96f9481d31807a3497340c9;hb=04da42770b0cc3bea8841972bfc9568299ece826;hp=124ddf684b5131eb6fd8e3f84b12dd52ebd64374;hpb=12f229ea8f6c8e20f8fd07906eafc853c4c354a9;p=platform%2Fkernel%2Fu-boot.git

diff --git a/drivers/video/rockchip/rk_edp.c b/drivers/video/rockchip/rk_edp.c
index 124ddf6..99b16cd 100644
--- a/drivers/video/rockchip/rk_edp.c
+++ b/drivers/video/rockchip/rk_edp.c
@@ -1,8 +1,7 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright (c) 2015 Google, Inc
  * Copyright 2014 Rockchip Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -10,18 +9,18 @@
 #include <display.h>
 #include <dm.h>
 #include <edid.h>
+#include <malloc.h>
 #include <panel.h>
 #include <regmap.h>
 #include <syscon.h>
 #include <asm/gpio.h>
 #include <asm/io.h>
-#include <asm/arch/clock.h>
-#include <asm/arch/edp_rk3288.h>
-#include <asm/arch/grf_rk3288.h>
+#include <asm/arch-rockchip/clock.h>
+#include <asm/arch-rockchip/edp_rk3288.h>
+#include <asm/arch-rockchip/grf_rk3288.h>
+#include <asm/arch-rockchip/hardware.h>
 #include <dt-bindings/clock/rk3288-cru.h>
 
-DECLARE_GLOBAL_DATA_PTR;
-
 #define MAX_CR_LOOP 5
 #define MAX_EQ_LOOP 5
 #define DP_LINK_STATUS_SIZE 6
@@ -998,19 +997,31 @@ static int rk_edp_ofdata_to_platdata(struct udevice *dev)
 {
 	struct rk_edp_priv *priv = dev_get_priv(dev);
 
-	priv->regs = (struct rk3288_edp *)dev_get_addr(dev);
+	priv->regs = dev_read_addr_ptr(dev);
 	priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF);
 
 	return 0;
 }
 
-int rk_edp_probe(struct udevice *dev)
+static int rk_edp_remove(struct udevice *dev)
+{
+	struct rk_edp_priv *priv = dev_get_priv(dev);
+	struct rk3288_edp *regs = priv->regs;
+
+	setbits_le32(&regs->video_ctl_1, VIDEO_MUTE);
+	clrbits_le32(&regs->video_ctl_1, VIDEO_EN);
+	clrbits_le32(&regs->sys_ctl_3, F_HPD | HPD_CTRL);
+	setbits_le32(&regs->func_en_1, SW_FUNC_EN_N);
+
+	return 0;
+}
+
+static int rk_edp_probe(struct udevice *dev)
 {
 	struct display_plat *uc_plat = dev_get_uclass_platdata(dev);
 	struct rk_edp_priv *priv = dev_get_priv(dev);
 	struct rk3288_edp *regs = priv->regs;
-	struct udevice *clk;
-	int periph;
+	struct clk clk;
 	int ret;
 
 	ret = uclass_get_device_by_phandle(UCLASS_PANEL, dev, "rockchip,panel",
@@ -1026,8 +1037,8 @@ int rk_edp_probe(struct udevice *dev)
 
 	ret = clk_get_by_index(dev, 1, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 0);
+		ret = clk_set_rate(&clk, 0);
+		clk_free(&clk);
 	}
 	if (ret) {
 		debug("%s: Failed to set EDP clock: ret=%d\n", __func__, ret);
@@ -1036,8 +1047,8 @@ int rk_edp_probe(struct udevice *dev)
 
 	ret = clk_get_by_index(uc_plat->src_dev, 0, &clk);
 	if (ret >= 0) {
-		periph = ret;
-		ret = clk_set_periph_rate(clk, periph, 192000000);
+		ret = clk_set_rate(&clk, 192000000);
+		clk_free(&clk);
 	}
 	if (ret < 0) {
 		debug("%s: Failed to set clock in source device '%s': ret=%d\n",
@@ -1081,5 +1092,6 @@ U_BOOT_DRIVER(dp_rockchip) = {
 	.ops	= &dp_rockchip_ops,
 	.ofdata_to_platdata	= rk_edp_ofdata_to_platdata,
 	.probe	= rk_edp_probe,
+	.remove	= rk_edp_remove,
 	.priv_auto_alloc_size	= sizeof(struct rk_edp_priv),
 };