X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fserial%2Fserial_zynq.c;h=d04c3990198f44bee07a34a4afb6788696d02bae;hb=41575d8e4c334df148c4cdd7c40cc825dc0fcaa1;hp=926ba51dbb4790271e21cb7f382a451bc7bae6ad;hpb=325c8d569ea9358ee3952984ec55961efab6d602;p=platform%2Fkernel%2Fu-boot.git diff --git a/drivers/serial/serial_zynq.c b/drivers/serial/serial_zynq.c index 926ba51..d04c399 100644 --- a/drivers/serial/serial_zynq.c +++ b/drivers/serial/serial_zynq.c @@ -1,29 +1,32 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * Copyright (C) 2012 Michal Simek * Copyright (C) 2011-2012 Xilinx, Inc. All rights reserved. - * - * SPDX-License-Identifier: GPL-2.0+ */ +#include #include +#include +#include #include #include +#include #include #include +#include +#include #include #include -#include -#include - -DECLARE_GLOBAL_DATA_PTR; +#include -#define ZYNQ_UART_SR_TXFULL 0x00000010 /* TX FIFO full */ -#define ZYNQ_UART_SR_RXEMPTY 0x00000002 /* RX FIFO empty */ +#define ZYNQ_UART_SR_TXACTIVE BIT(11) /* TX active */ +#define ZYNQ_UART_SR_TXFULL BIT(4) /* TX FIFO full */ +#define ZYNQ_UART_SR_RXEMPTY BIT(1) /* RX FIFO empty */ -#define ZYNQ_UART_CR_TX_EN 0x00000010 /* TX enabled */ -#define ZYNQ_UART_CR_RX_EN 0x00000004 /* RX enabled */ -#define ZYNQ_UART_CR_TXRST 0x00000002 /* TX logic reset */ -#define ZYNQ_UART_CR_RXRST 0x00000001 /* RX logic reset */ +#define ZYNQ_UART_CR_TX_EN BIT(4) /* TX enabled */ +#define ZYNQ_UART_CR_RX_EN BIT(2) /* RX enabled */ +#define ZYNQ_UART_CR_TXRST BIT(1) /* TX logic reset */ +#define ZYNQ_UART_CR_RXRST BIT(0) /* RX logic reset */ #define ZYNQ_UART_MR_PARITY_NONE 0x00000020 /* No parity mode */ @@ -38,12 +41,11 @@ struct uart_zynq { u32 baud_rate_divider; /* 0x34 - Baud Rate Divider [7:0] */ }; -static struct uart_zynq *uart_zynq_ports[2] = { - [0] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR0, - [1] = (struct uart_zynq *)ZYNQ_SERIAL_BASEADDR1, +struct zynq_uart_platdata { + struct uart_zynq *regs; }; -/* Set up the baud rate in gd struct */ +/* Set up the baud rate */ static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, unsigned long clock, unsigned long baud) { @@ -84,15 +86,6 @@ static void _uart_zynq_serial_setbrg(struct uart_zynq *regs, writel(bgen, ®s->baud_rate_gen); } -/* Set up the baud rate in gd struct */ -static void uart_zynq_serial_setbrg(const int port) -{ - unsigned long clock = get_uart_clk(port); - struct uart_zynq *regs = uart_zynq_ports[port]; - - return _uart_zynq_serial_setbrg(regs, clock, gd->baudrate); -} - /* Initialize the UART, with...some settings. */ static void _uart_zynq_serial_init(struct uart_zynq *regs) { @@ -102,20 +95,6 @@ static void _uart_zynq_serial_init(struct uart_zynq *regs) writel(ZYNQ_UART_MR_PARITY_NONE, ®s->mode); /* 8 bit, no parity */ } -/* Initialize the UART, with...some settings. */ -static int uart_zynq_serial_init(const int port) -{ - struct uart_zynq *regs = uart_zynq_ports[port]; - - if (!regs) - return -1; - - _uart_zynq_serial_init(regs); - uart_zynq_serial_setbrg(port); - - return 0; -} - static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) { if (readl(®s->channel_sts) & ZYNQ_UART_SR_TXFULL) @@ -126,109 +105,120 @@ static int _uart_zynq_serial_putc(struct uart_zynq *regs, const char c) return 0; } -static void uart_zynq_serial_putc(const char c, const int port) +static int zynq_serial_setbrg(struct udevice *dev, int baudrate) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_platdata *platdata = dev_get_platdata(dev); + unsigned long clock; - while (_uart_zynq_serial_putc(regs, c) == -EAGAIN) - WATCHDOG_RESET(); + int ret; + struct clk clk; - if (c == '\n') { - while (_uart_zynq_serial_putc(regs, '\r') == -EAGAIN) - WATCHDOG_RESET(); + ret = clk_get_by_index(dev, 0, &clk); + if (ret < 0) { + dev_err(dev, "failed to get clock\n"); + return ret; } -} -static void uart_zynq_serial_puts(const char *s, const int port) -{ - while (*s) - uart_zynq_serial_putc(*s++, port); + clock = clk_get_rate(&clk); + if (IS_ERR_VALUE(clock)) { + dev_err(dev, "failed to get rate\n"); + return clock; + } + debug("%s: CLK %ld\n", __func__, clock); + + ret = clk_enable(&clk); + if (ret && ret != -ENOSYS) { + dev_err(dev, "failed to enable clock\n"); + return ret; + } + + _uart_zynq_serial_setbrg(platdata->regs, clock, baudrate); + + return 0; } -static int uart_zynq_serial_tstc(const int port) +static int zynq_serial_probe(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_zynq *regs = platdata->regs; + u32 val; + + /* No need to reinitialize the UART if TX already enabled */ + val = readl(®s->control); + if (val & ZYNQ_UART_CR_TX_EN) + return 0; + + _uart_zynq_serial_init(platdata->regs); - return (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) == 0; + return 0; } -static int uart_zynq_serial_getc(const int port) +static int zynq_serial_getc(struct udevice *dev) { - struct uart_zynq *regs = uart_zynq_ports[port]; + struct zynq_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_zynq *regs = platdata->regs; + + if (readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY) + return -EAGAIN; - while (!uart_zynq_serial_tstc(port)) - WATCHDOG_RESET(); return readl(®s->tx_rx_fifo); } -/* Multi serial device functions */ -#define DECLARE_PSSERIAL_FUNCTIONS(port) \ - static int uart_zynq##port##_init(void) \ - { return uart_zynq_serial_init(port); } \ - static void uart_zynq##port##_setbrg(void) \ - { return uart_zynq_serial_setbrg(port); } \ - static int uart_zynq##port##_getc(void) \ - { return uart_zynq_serial_getc(port); } \ - static int uart_zynq##port##_tstc(void) \ - { return uart_zynq_serial_tstc(port); } \ - static void uart_zynq##port##_putc(const char c) \ - { uart_zynq_serial_putc(c, port); } \ - static void uart_zynq##port##_puts(const char *s) \ - { uart_zynq_serial_puts(s, port); } - -/* Serial device descriptor */ -#define INIT_PSSERIAL_STRUCTURE(port, __name) { \ - .name = __name, \ - .start = uart_zynq##port##_init, \ - .stop = NULL, \ - .setbrg = uart_zynq##port##_setbrg, \ - .getc = uart_zynq##port##_getc, \ - .tstc = uart_zynq##port##_tstc, \ - .putc = uart_zynq##port##_putc, \ - .puts = uart_zynq##port##_puts, \ -} +static int zynq_serial_putc(struct udevice *dev, const char ch) +{ + struct zynq_uart_platdata *platdata = dev_get_platdata(dev); -DECLARE_PSSERIAL_FUNCTIONS(0); -static struct serial_device uart_zynq_serial0_device = - INIT_PSSERIAL_STRUCTURE(0, "ttyPS0"); -DECLARE_PSSERIAL_FUNCTIONS(1); -static struct serial_device uart_zynq_serial1_device = - INIT_PSSERIAL_STRUCTURE(1, "ttyPS1"); + return _uart_zynq_serial_putc(platdata->regs, ch); +} -__weak struct serial_device *default_serial_console(void) +static int zynq_serial_pending(struct udevice *dev, bool input) { - const void *blob = gd->fdt_blob; - int node; - unsigned int base_addr; - - node = fdt_path_offset(blob, "serial0"); - if (node < 0) - return NULL; + struct zynq_uart_platdata *platdata = dev_get_platdata(dev); + struct uart_zynq *regs = platdata->regs; - base_addr = fdtdec_get_addr(blob, node, "reg"); - if (base_addr == FDT_ADDR_T_NONE) - return NULL; + if (input) + return !(readl(®s->channel_sts) & ZYNQ_UART_SR_RXEMPTY); + else + return !!(readl(®s->channel_sts) & ZYNQ_UART_SR_TXACTIVE); +} - if (base_addr == ZYNQ_SERIAL_BASEADDR0) - return &uart_zynq_serial0_device; +static int zynq_serial_ofdata_to_platdata(struct udevice *dev) +{ + struct zynq_uart_platdata *platdata = dev_get_platdata(dev); - if (base_addr == ZYNQ_SERIAL_BASEADDR1) - return &uart_zynq_serial1_device; + platdata->regs = (struct uart_zynq *)dev_read_addr(dev); + if (IS_ERR(platdata->regs)) + return PTR_ERR(platdata->regs); - return NULL; + return 0; } -void zynq_serial_initialize(void) -{ - serial_register(&uart_zynq_serial0_device); - serial_register(&uart_zynq_serial1_device); -} +static const struct dm_serial_ops zynq_serial_ops = { + .putc = zynq_serial_putc, + .pending = zynq_serial_pending, + .getc = zynq_serial_getc, + .setbrg = zynq_serial_setbrg, +}; -#ifdef CONFIG_DEBUG_UART_ZYNQ +static const struct udevice_id zynq_serial_ids[] = { + { .compatible = "xlnx,xuartps" }, + { .compatible = "cdns,uart-r1p8" }, + { .compatible = "cdns,uart-r1p12" }, + { } +}; -#include +U_BOOT_DRIVER(serial_zynq) = { + .name = "serial_zynq", + .id = UCLASS_SERIAL, + .of_match = zynq_serial_ids, + .ofdata_to_platdata = zynq_serial_ofdata_to_platdata, + .platdata_auto = sizeof(struct zynq_uart_platdata), + .probe = zynq_serial_probe, + .ops = &zynq_serial_ops, +}; -void _debug_uart_init(void) +#ifdef CONFIG_DEBUG_UART_ZYNQ +static inline void _debug_uart_init(void) { struct uart_zynq *regs = (struct uart_zynq *)CONFIG_DEBUG_UART_BASE;