X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fram%2Frockchip%2Fsdram_rk3188.c;h=ad9f936df55a775a2f9ad5c7768b088b77405eca;hb=0fbb96964b8574ca8012b2022cd0e431977fd340;hp=d3e4316ef019b44ef3efafaa9023f037315b8144;hpb=71d96eb99e79ba69f47504b72cd54ce121eca422;p=platform%2Fkernel%2Fu-boot.git

diff --git a/drivers/ram/rockchip/sdram_rk3188.c b/drivers/ram/rockchip/sdram_rk3188.c
index d3e4316..ad9f936 100644
--- a/drivers/ram/rockchip/sdram_rk3188.c
+++ b/drivers/ram/rockchip/sdram_rk3188.c
@@ -11,6 +11,9 @@
 #include <dm.h>
 #include <dt-structs.h>
 #include <errno.h>
+#include <hang.h>
+#include <init.h>
+#include <log.h>
 #include <ram.h>
 #include <regmap.h>
 #include <syscon.h>
@@ -22,6 +25,7 @@
 #include <asm/arch-rockchip/pmu_rk3188.h>
 #include <asm/arch-rockchip/sdram.h>
 #include <asm/arch-rockchip/sdram_rk3288.h>
+#include <linux/delay.h>
 #include <linux/err.h>
 
 struct chan_info {
@@ -634,12 +638,12 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
 
 	/* Detect col */
 	for (col = 11; col >= 9; col--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE +
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE +
 			(1 << (col + sdram_params->ch[channel].bw - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (col == 8) {
@@ -656,11 +660,11 @@ static int sdram_col_row_detect(struct dram_info *dram, int channel,
 	move_to_access_state(chan);
 	/* Detect row, max 15,min13 in rk3188*/
 	for (row = 16; row >= 13; row--) {
-		writel(0, CONFIG_SYS_SDRAM_BASE);
-		addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
+		writel(0, CFG_SYS_SDRAM_BASE);
+		addr = CFG_SYS_SDRAM_BASE + (1 << (row + 15 - 1));
 		writel(TEST_PATTEN, addr);
 		if ((readl(addr) == TEST_PATTEN) &&
-		    (readl(CONFIG_SYS_SDRAM_BASE) == 0))
+		    (readl(CFG_SYS_SDRAM_BASE) == 0))
 			break;
 	}
 	if (row == 12) {
@@ -758,7 +762,7 @@ static int sdram_init(struct dram_info *dram,
 		 * CS1, n=2
 		 * CS0 & CS1, n = 3
 		 */
-		sdram_params->ch[channel].rank = 2,
+		sdram_params->ch[channel].rank = 2;
 		clrsetbits_le32(&publ->pgcr, 0xF << 18,
 				(sdram_params->ch[channel].rank | 1) << 18);
 
@@ -805,17 +809,19 @@ error:
 static int setup_sdram(struct udevice *dev)
 {
 	struct dram_info *priv = dev_get_priv(dev);
-	struct rk3188_sdram_params *params = dev_get_platdata(dev);
+	struct rk3188_sdram_params *params = dev_get_plat(dev);
 
 	return sdram_init(priv, params);
 }
 
-static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
+static int rk3188_dmc_of_to_plat(struct udevice *dev)
 {
-#if !CONFIG_IS_ENABLED(OF_PLATDATA)
-	struct rk3188_sdram_params *params = dev_get_platdata(dev);
+	struct rk3188_sdram_params *params = dev_get_plat(dev);
 	int ret;
 
+	if (!CONFIG_IS_ENABLED(OF_REAL))
+		return 0;
+
 	/* rk3188 supports only one-channel */
 	params->num_channels = 1;
 	ret = dev_read_u32_array(dev, "rockchip,pctl-timing",
@@ -842,16 +848,15 @@ static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev)
 	ret = regmap_init_mem(dev_ofnode(dev), &params->map);
 	if (ret)
 		return ret;
-#endif
 
 	return 0;
 }
 #endif /* CONFIG_SPL_BUILD */
 
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-static int conv_of_platdata(struct udevice *dev)
+static int conv_of_plat(struct udevice *dev)
 {
-	struct rk3188_sdram_params *plat = dev_get_platdata(dev);
+	struct rk3188_sdram_params *plat = dev_get_plat(dev);
 	struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat;
 	int ret;
 
@@ -862,9 +867,8 @@ static int conv_of_platdata(struct udevice *dev)
 	memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base));
 	/* rk3188 supports dual-channel, set default channel num to 2 */
 	plat->num_channels = 1;
-	ret = regmap_init_mem_platdata(dev, of_plat->reg,
-				       ARRAY_SIZE(of_plat->reg) / 2,
-				       &plat->map);
+	ret = regmap_init_mem_plat(dev, of_plat->reg, sizeof(of_plat->reg[0]),
+				   ARRAY_SIZE(of_plat->reg) / 2, &plat->map);
 	if (ret)
 		return ret;
 
@@ -875,7 +879,7 @@ static int conv_of_platdata(struct udevice *dev)
 static int rk3188_dmc_probe(struct udevice *dev)
 {
 #ifdef CONFIG_SPL_BUILD
-	struct rk3188_sdram_params *plat = dev_get_platdata(dev);
+	struct rk3188_sdram_params *plat = dev_get_plat(dev);
 	struct regmap *map;
 	struct udevice *dev_clk;
 	int ret;
@@ -886,7 +890,7 @@ static int rk3188_dmc_probe(struct udevice *dev)
 
 #ifdef CONFIG_SPL_BUILD
 #if CONFIG_IS_ENABLED(OF_PLATDATA)
-	ret = conv_of_platdata(dev);
+	ret = conv_of_plat(dev);
 	if (ret)
 		return ret;
 #endif
@@ -915,7 +919,7 @@ static int rk3188_dmc_probe(struct udevice *dev)
 	if (ret)
 		return ret;
 #else
-	priv->info.base = CONFIG_SYS_SDRAM_BASE;
+	priv->info.base = CFG_SYS_SDRAM_BASE;
 	priv->info.size = rockchip_sdram_size(
 				(phys_addr_t)&priv->pmu->sys_reg[2]);
 #endif
@@ -941,17 +945,17 @@ static const struct udevice_id rk3188_dmc_ids[] = {
 	{ }
 };
 
-U_BOOT_DRIVER(dmc_rk3188) = {
+U_BOOT_DRIVER(rockchip_rk3188_dmc) = {
 	.name = "rockchip_rk3188_dmc",
 	.id = UCLASS_RAM,
 	.of_match = rk3188_dmc_ids,
 	.ops = &rk3188_dmc_ops,
 #ifdef CONFIG_SPL_BUILD
-	.ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata,
+	.of_to_plat = rk3188_dmc_of_to_plat,
 #endif
 	.probe = rk3188_dmc_probe,
-	.priv_auto_alloc_size = sizeof(struct dram_info),
+	.priv_auto	= sizeof(struct dram_info),
 #ifdef CONFIG_SPL_BUILD
-	.platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params),
+	.plat_auto	= sizeof(struct rk3188_sdram_params),
 #endif
 };