X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fpci%2Ffsl_pci_init.c;h=375b8549c595a256e9088cb7ddbb423c5d3c5cb2;hb=83d290c56fab2d38cd1ab4c4cc7099559c1d5046;hp=152045ed93d26230581a8d641d94eea11420e2ae;hpb=5066e62847bddf6030262ade2aa3e7bcdc930037;p=platform%2Fkernel%2Fu-boot.git

diff --git a/drivers/pci/fsl_pci_init.c b/drivers/pci/fsl_pci_init.c
index 152045e..375b854 100644
--- a/drivers/pci/fsl_pci_init.c
+++ b/drivers/pci/fsl_pci_init.c
@@ -1,7 +1,6 @@
+// SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2007-2012 Freescale Semiconductor, Inc.
- *
- * SPDX-License-Identifier:	GPL-2.0+
  */
 
 #include <common.h>
@@ -390,7 +389,7 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	/* boot from PCIE --master */
-	char *s = getenv("bootmaster");
+	char *s = env_get("bootmaster");
 	char pcie[6];
 	sprintf(pcie, "PCIE%d", pci_info->pci_num);
 
@@ -543,6 +542,13 @@ void fsl_pci_init(struct pci_controller *hose, struct fsl_pci_info *pci_info)
 		pciauto_prescan_setup_bridge(hose, dev, hose->current_busno);
 	}
 
+#ifdef CONFIG_SYS_FSL_ERRATUM_A007815
+	/* The Read-Only Write Enable bit defaults to 1 instead of 0.
+	 * Set to 0 to protect the read-only registers.
+	 */
+	clrbits_be32(&pci->dbi_ro_wr_en, 0x01);
+#endif
+
 	/* Use generic setup_device to initialize standard pci regs,
 	 * but do not allocate any windows since any BAR found (such
 	 * as PCSRBAR) is not in this cpu's memory space.
@@ -666,7 +672,7 @@ int fsl_pci_init_port(struct fsl_pci_info *pci_info,
 #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER
 	} else {
 		/* boot from PCIE --master releases slave's core 0 */
-		char *s = getenv("bootmaster");
+		char *s = env_get("bootmaster");
 		char pcie[6];
 		sprintf(pcie, "PCIE%d", pci_info->pci_num);
 
@@ -697,8 +703,14 @@ void fsl_pci_config_unlock(struct pci_controller *hose)
 	pcie_cap_pos = pci_hose_find_capability(hose, dev, PCI_CAP_ID_EXP);
 	pci_hose_read_config_byte(hose, dev, pcie_cap_pos, &pcie_cap);
 	if (pcie_cap != 0x0) {
+		ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)hose->cfg_addr;
+		u32 block_rev = in_be32(&pci->block_rev1);
 		/* PCIe - set CFG_READY bit of Configuration Ready Register */
-		pci_hose_write_config_byte(hose, dev, FSL_PCIE_CFG_RDY, 0x1);
+		if (block_rev >= PEX_IP_BLK_REV_3_0)
+			setbits_be32(&pci->config, FSL_PCIE_V3_CFG_RDY);
+		else
+			pci_hose_write_config_byte(hose, dev,
+						   FSL_PCIE_CFG_RDY, 0x1);
 	} else {
 		/* PCI - clear ACL bit of PBFR */
 		pci_hose_read_config_word(hose, dev, FSL_PCI_PBFR, &pbfr);
@@ -873,7 +885,7 @@ int fsl_pcie_init_board(int busno)
 #endif
 
 #ifdef CONFIG_OF_BOARD_SETUP
-#include <libfdt.h>
+#include <linux/libfdt.h>
 #include <fdt_support.h>
 
 void ft_fsl_pci_setup(void *blob, const char *pci_compat,