X-Git-Url: http://review.tizen.org/git/?a=blobdiff_plain;f=drivers%2Fnet%2Fsun8i_emac.c;h=c9798445c7dd1a675f7cba2034fef3e850fff1c3;hb=9450ab2ba8d720bd9f73bccc0af2e2b5a2c2aaf1;hp=91570a29106f6d5ccd8ba80be7c976d097c8e8d9;hpb=78ad7157886badef2d69e264c366dbdd2eac040f;p=platform%2Fkernel%2Fu-boot.git diff --git a/drivers/net/sun8i_emac.c b/drivers/net/sun8i_emac.c index 91570a2..c979844 100644 --- a/drivers/net/sun8i_emac.c +++ b/drivers/net/sun8i_emac.c @@ -1,9 +1,8 @@ +// SPDX-License-Identifier: GPL-2.0+ /* * (C) Copyright 2016 * Author: Amit Singh Tomar, amittomer25@gmail.com * - * SPDX-License-Identifier: GPL-2.0+ - * * Ethernet driver for H3/A64/A83T based SoC's * * It is derived from the work done by @@ -21,6 +20,10 @@ #include #include #include +#include +#ifdef CONFIG_DM_GPIO +#include +#endif #define MDIO_CMD_MII_BUSY BIT(0) #define MDIO_CMD_MII_WRITE BIT(1) @@ -57,16 +60,19 @@ #define SC_ETCS_MASK GENMASK(1, 0) #define SC_ETCS_EXT_GMII 0x1 #define SC_ETCS_INT_GMII 0x2 +#define SC_ETXDC_MASK GENMASK(12, 10) +#define SC_ETXDC_OFFSET 10 +#define SC_ERXDC_MASK GENMASK(9, 5) +#define SC_ERXDC_OFFSET 5 #define CONFIG_MDIO_TIMEOUT (3 * CONFIG_SYS_HZ) #define AHB_GATE_OFFSET_EPHY 0 -#if defined(CONFIG_MACH_SUN8I_H3) -#define SUN8I_GPD8_GMAC 2 -#else -#define SUN8I_GPD8_GMAC 4 -#endif +/* IO mux settings */ +#define SUN8I_IOMUX_H3 2 +#define SUN8I_IOMUX_R40 5 +#define SUN8I_IOMUX 4 /* H3/A64 EMAC Register's offset */ #define EMAC_CTL0 0x00 @@ -96,6 +102,7 @@ enum emac_variant { A83T_EMAC = 1, H3_EMAC, A64_EMAC, + R40_GMAC, }; struct emac_dma_desc { @@ -128,11 +135,24 @@ struct emac_eth_dev { phys_addr_t sysctl_reg; struct phy_device *phydev; struct mii_dev *bus; +#ifdef CONFIG_DM_GPIO + struct gpio_desc reset_gpio; +#endif }; + +struct sun8i_eth_pdata { + struct eth_pdata eth_pdata; + u32 reset_delays[3]; + int tx_delay_ps; + int rx_delay_ps; +}; + + static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) { - struct emac_eth_dev *priv = bus->priv; + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); ulong start; u32 miiaddr = 0; int timeout = CONFIG_MDIO_TIMEOUT; @@ -164,7 +184,8 @@ static int sun8i_mdio_read(struct mii_dev *bus, int addr, int devad, int reg) static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, u16 val) { - struct emac_eth_dev *priv = bus->priv; + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); ulong start; u32 miiaddr = 0; int ret = -1, timeout = CONFIG_MDIO_TIMEOUT; @@ -180,8 +201,8 @@ static int sun8i_mdio_write(struct mii_dev *bus, int addr, int devad, int reg, miiaddr |= MDIO_CMD_MII_WRITE; miiaddr |= MDIO_CMD_MII_BUSY; - writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); writel(val, priv->mac_reg + EMAC_MII_DATA); + writel(miiaddr, priv->mac_reg + EMAC_MII_CMD); start = get_timer(0); while (get_timer(start) < timeout) { @@ -258,12 +279,16 @@ static int sun8i_emac_set_syscon_ephy(struct emac_eth_dev *priv, u32 *reg) return 0; } -static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) +static int sun8i_emac_set_syscon(struct sun8i_eth_pdata *pdata, + struct emac_eth_dev *priv) { int ret; u32 reg; - reg = readl(priv->sysctl_reg); + reg = readl(priv->sysctl_reg + 0x30); + + if (priv->variant == R40_GMAC) + return 0; if (priv->variant == H3_EMAC) { ret = sun8i_emac_set_syscon_ephy(priv, ®); @@ -294,7 +319,15 @@ static int sun8i_emac_set_syscon(struct emac_eth_dev *priv) return -EINVAL; } - writel(reg, priv->sysctl_reg); + if (pdata->tx_delay_ps) + reg |= ((pdata->tx_delay_ps / 100) << SC_ETXDC_OFFSET) + & SC_ETXDC_MASK; + + if (pdata->rx_delay_ps) + reg |= ((pdata->rx_delay_ps / 100) << SC_ERXDC_OFFSET) + & SC_ERXDC_MASK; + + writel(reg, priv->sysctl_reg + 0x30); return 0; } @@ -416,7 +449,7 @@ static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) tx_descs_init(priv); /* PHY Start Up */ - genphy_parse_link(priv->phydev); + phy_startup(priv->phydev); sun8i_adjust_link(priv, priv->phydev); @@ -438,11 +471,12 @@ static int _sun8i_emac_eth_init(struct emac_eth_dev *priv, u8 *enetaddr) static int parse_phy_pins(struct udevice *dev) { + struct emac_eth_dev *priv = dev_get_priv(dev); int offset; const char *pin_name; - int drive, pull, i; + int drive, pull = SUN4I_PINCTRL_NO_PULL, i; - offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, + offset = fdtdec_lookup_phandle(gd->fdt_blob, dev_of_offset(dev), "pinctrl-0"); if (offset < 0) { printf("WARNING: emac: cannot find pinctrl-0 node\n"); @@ -450,30 +484,50 @@ static int parse_phy_pins(struct udevice *dev) } drive = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,drive", 4); - pull = fdt_getprop_u32_default_node(gd->fdt_blob, offset, 0, - "allwinner,pull", 0); + "drive-strength", ~0); + if (drive != ~0) { + if (drive <= 10) + drive = SUN4I_PINCTRL_10_MA; + else if (drive <= 20) + drive = SUN4I_PINCTRL_20_MA; + else if (drive <= 30) + drive = SUN4I_PINCTRL_30_MA; + else + drive = SUN4I_PINCTRL_40_MA; + } + + if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-up", NULL)) + pull = SUN4I_PINCTRL_PULL_UP; + else if (fdt_get_property(gd->fdt_blob, offset, "bias-pull-down", NULL)) + pull = SUN4I_PINCTRL_PULL_DOWN; + for (i = 0; ; i++) { int pin; pin_name = fdt_stringlist_get(gd->fdt_blob, offset, - "allwinner,pins", i, NULL); + "pins", i, NULL); if (!pin_name) break; - if (pin_name[0] != 'P') - continue; - pin = (pin_name[1] - 'A') << 5; - if (pin >= 26 << 5) + + pin = sunxi_name_to_gpio(pin_name); + if (pin < 0) continue; - pin += simple_strtol(&pin_name[2], NULL, 10); - sunxi_gpio_set_cfgpin(pin, SUN8I_GPD8_GMAC); - sunxi_gpio_set_drv(pin, drive); - sunxi_gpio_set_pull(pin, pull); + if (priv->variant == H3_EMAC) + sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_H3); + else if (priv->variant == R40_GMAC) + sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX_R40); + else + sunxi_gpio_set_cfgpin(pin, SUN8I_IOMUX); + + if (drive != ~0) + sunxi_gpio_set_drv(pin, drive); + if (pull != ~0) + sunxi_gpio_set_pull(pin, pull); } if (!i) { - printf("WARNING: emac: cannot find allwinner,pins property\n"); + printf("WARNING: emac: cannot find pins property\n"); return -2; } @@ -589,22 +643,76 @@ static void sun8i_emac_board_setup(struct emac_eth_dev *priv) { struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; - if (priv->use_internal_phy) { - /* Set clock gating for ephy */ - setbits_le32(&ccm->bus_gate4, BIT(AHB_GATE_OFFSET_EPHY)); + if (priv->variant == H3_EMAC) { + /* Only H3/H5 have clock controls for internal EPHY */ + if (priv->use_internal_phy) { + /* Set clock gating for ephy */ + setbits_le32(&ccm->bus_gate4, + BIT(AHB_GATE_OFFSET_EPHY)); + + /* Deassert EPHY */ + setbits_le32(&ccm->ahb_reset2_cfg, + BIT(AHB_RESET_OFFSET_EPHY)); + } + } - /* Deassert EPHY */ - setbits_le32(&ccm->ahb_reset2_cfg, BIT(AHB_RESET_OFFSET_EPHY)); + if (priv->variant == R40_GMAC) { + /* Set clock gating for emac */ + setbits_le32(&ccm->ahb_reset1_cfg, BIT(AHB_RESET_OFFSET_GMAC)); + + /* De-assert EMAC */ + setbits_le32(&ccm->ahb_gate1, BIT(AHB_GATE_OFFSET_GMAC)); + + /* Select RGMII for R40 */ + setbits_le32(&ccm->gmac_clk_cfg, + CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII | + CCM_GMAC_CTRL_GPIT_RGMII); + setbits_le32(&ccm->gmac_clk_cfg, + CCM_GMAC_CTRL_TX_CLK_DELAY(CONFIG_GMAC_TX_DELAY)); + } else { + /* Set clock gating for emac */ + setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); + + /* De-assert EMAC */ + setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); } +} + +#if defined(CONFIG_DM_GPIO) +static int sun8i_mdio_reset(struct mii_dev *bus) +{ + struct udevice *dev = bus->priv; + struct emac_eth_dev *priv = dev_get_priv(dev); + struct sun8i_eth_pdata *pdata = dev_get_platdata(dev); + int ret; + + if (!dm_gpio_is_valid(&priv->reset_gpio)) + return 0; + + /* reset the phy */ + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[0]); + + ret = dm_gpio_set_value(&priv->reset_gpio, 1); + if (ret) + return ret; - /* Set clock gating for emac */ - setbits_le32(&ccm->ahb_gate0, BIT(AHB_GATE_OFFSET_GMAC)); + udelay(pdata->reset_delays[1]); - /* De-assert EMAC */ - setbits_le32(&ccm->ahb_reset0_cfg, BIT(AHB_RESET_OFFSET_GMAC)); + ret = dm_gpio_set_value(&priv->reset_gpio, 0); + if (ret) + return ret; + + udelay(pdata->reset_delays[2]); + + return 0; } +#endif -static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) +static int sun8i_mdio_init(const char *name, struct udevice *priv) { struct mii_dev *bus = mdio_alloc(); @@ -617,6 +725,9 @@ static int sun8i_mdio_init(const char *name, struct emac_eth_dev *priv) bus->write = sun8i_mdio_write; snprintf(bus->name, sizeof(bus->name), name); bus->priv = (void *)priv; +#if defined(CONFIG_DM_GPIO) + bus->reset = sun8i_mdio_reset; +#endif return mdio_register(bus); } @@ -688,15 +799,16 @@ static void sun8i_emac_eth_stop(struct udevice *dev) static int sun8i_emac_eth_probe(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); + struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); priv->mac_reg = (void *)pdata->iobase; sun8i_emac_board_setup(priv); - sun8i_emac_set_syscon(priv); + sun8i_emac_set_syscon(sun8i_pdata, priv); - sun8i_mdio_init(dev->name, priv); + sun8i_mdio_init(dev->name, dev); priv->bus = miiphy_get_dev_by_name(dev->name); return sun8i_phy_init(priv, dev); @@ -713,25 +825,64 @@ static const struct eth_ops sun8i_emac_eth_ops = { static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) { - struct eth_pdata *pdata = dev_get_platdata(dev); + struct sun8i_eth_pdata *sun8i_pdata = dev_get_platdata(dev); + struct eth_pdata *pdata = &sun8i_pdata->eth_pdata; struct emac_eth_dev *priv = dev_get_priv(dev); const char *phy_mode; + const fdt32_t *reg; + int node = dev_of_offset(dev); int offset = 0; +#ifdef CONFIG_DM_GPIO + int reset_flags = GPIOD_IS_OUT; + int ret = 0; +#endif + + pdata->iobase = devfdt_get_addr(dev); + if (pdata->iobase == FDT_ADDR_T_NONE) { + debug("%s: Cannot find MAC base address\n", __func__); + return -EINVAL; + } + + priv->variant = dev_get_driver_data(dev); + + if (!priv->variant) { + printf("%s: Missing variant\n", __func__); + return -EINVAL; + } - pdata->iobase = dev_get_addr_name(dev, "emac"); - priv->sysctl_reg = dev_get_addr_name(dev, "syscon"); + if (priv->variant != R40_GMAC) { + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "syscon"); + if (offset < 0) { + debug("%s: cannot find syscon node\n", __func__); + return -EINVAL; + } + reg = fdt_getprop(gd->fdt_blob, offset, "reg", NULL); + if (!reg) { + debug("%s: cannot find reg property in syscon node\n", + __func__); + return -EINVAL; + } + priv->sysctl_reg = fdt_translate_address((void *)gd->fdt_blob, + offset, reg); + if (priv->sysctl_reg == FDT_ADDR_T_NONE) { + debug("%s: Cannot find syscon base address\n", + __func__); + return -EINVAL; + } + } pdata->phy_interface = -1; priv->phyaddr = -1; priv->use_internal_phy = false; - offset = fdtdec_lookup_phandle(gd->fdt_blob, dev->of_offset, - "phy"); - if (offset > 0) - priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", - -1); + offset = fdtdec_lookup_phandle(gd->fdt_blob, node, "phy-handle"); + if (offset < 0) { + debug("%s: Cannot find PHY address\n", __func__); + return -EINVAL; + } + priv->phyaddr = fdtdec_get_int(gd->fdt_blob, offset, "reg", -1); - phy_mode = fdt_getprop(gd->fdt_blob, dev->of_offset, "phy-mode", NULL); + phy_mode = fdt_getprop(gd->fdt_blob, node, "phy-mode", NULL); if (phy_mode) pdata->phy_interface = phy_get_interface_by_name(phy_mode); @@ -742,17 +893,12 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) return -EINVAL; } - priv->variant = dev_get_driver_data(dev); - - if (!priv->variant) { - printf("%s: Missing variant '%s'\n", __func__, - (char *)priv->variant); - return -EINVAL; - } - if (priv->variant == H3_EMAC) { - if (fdt_getprop(gd->fdt_blob, dev->of_offset, - "allwinner,use-internal-phy", NULL)) + int parent = fdt_parent_offset(gd->fdt_blob, offset); + + if (parent >= 0 && + !fdt_node_check_compatible(gd->fdt_blob, parent, + "allwinner,sun8i-h3-mdio-internal")) priv->use_internal_phy = true; } @@ -761,6 +907,35 @@ static int sun8i_emac_eth_ofdata_to_platdata(struct udevice *dev) if (!priv->use_internal_phy) parse_phy_pins(dev); + sun8i_pdata->tx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, + "allwinner,tx-delay-ps", 0); + if (sun8i_pdata->tx_delay_ps < 0 || sun8i_pdata->tx_delay_ps > 700) + printf("%s: Invalid TX delay value %d\n", __func__, + sun8i_pdata->tx_delay_ps); + + sun8i_pdata->rx_delay_ps = fdtdec_get_int(gd->fdt_blob, node, + "allwinner,rx-delay-ps", 0); + if (sun8i_pdata->rx_delay_ps < 0 || sun8i_pdata->rx_delay_ps > 3100) + printf("%s: Invalid RX delay value %d\n", __func__, + sun8i_pdata->rx_delay_ps); + +#ifdef CONFIG_DM_GPIO + if (fdtdec_get_bool(gd->fdt_blob, dev_of_offset(dev), + "snps,reset-active-low")) + reset_flags |= GPIOD_ACTIVE_LOW; + + ret = gpio_request_by_name(dev, "snps,reset-gpio", 0, + &priv->reset_gpio, reset_flags); + + if (ret == 0) { + ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), + "snps,reset-delays-us", + sun8i_pdata->reset_delays, 3); + } else if (ret == -ENOENT) { + ret = 0; + } +#endif + return 0; } @@ -770,6 +945,8 @@ static const struct udevice_id sun8i_emac_eth_ids[] = { .data = (uintptr_t)A64_EMAC }, {.compatible = "allwinner,sun8i-a83t-emac", .data = (uintptr_t)A83T_EMAC }, + {.compatible = "allwinner,sun8i-r40-gmac", + .data = (uintptr_t)R40_GMAC }, { } }; @@ -781,6 +958,6 @@ U_BOOT_DRIVER(eth_sun8i_emac) = { .probe = sun8i_emac_eth_probe, .ops = &sun8i_emac_eth_ops, .priv_auto_alloc_size = sizeof(struct emac_eth_dev), - .platdata_auto_alloc_size = sizeof(struct eth_pdata), + .platdata_auto_alloc_size = sizeof(struct sun8i_eth_pdata), .flags = DM_FLAG_ALLOC_PRIV_DMA, };